Low Power Electronics Exploring the Fundamental Limits of Computation

1
Low Power ElectronicsExploring the Fundamental
Limits of Computation
http//www.eng.fsu.edu/mpf

• Dr. Michael P. Frank
• Invited Videoconference TalkPragyaa Festival
• Shri Guru Gobind Singhji Institute of Engineering
  and Technology, Vishnupuri, Nanded, India
• April 3, 2005

2
Abstract of Talk

• The electronics industry is rapidly approaching
  various fundamental physical limits to the energy
  efficiency of conventional digital technologies.
• As a result, the performance of practical digital
  systems based on conventional technology must
  level off within at most 1-3 decades.
• Our generation will be forced to deal with the
  consequences!
• There is only one potential way to circumvent all
  these limits that is consistent with the known
  laws of physics.
• Namely To develop highly reversible computing
  technologies.
• These recycle and reuse most of the logic signal
  energy.
• Reversible computing opens the door to
  potentially unlimited future improvements in
  computer efficiency.
• This could have enormous potential implications!
• But, to develop reversible computing into a fully
  practical technology is a very challenging
  engineering problem
• The worlds brightest, most creative people will
  be needed to solve it!
• With hard work, maybe you will be the one to make
  the key breakthroughs!

3
Computer Performance versus Power

• Computer performance ? is defined as the rate at
  which operations (of some standard size) are
  performed
• i.e., the number nop of operations per unit t of
  time, ? nop/t.
• Example Boolean logic operations per second.
• In contrast, power P in physics refers to an
  amount E of energy per unit of time t, that is, P
  E/t.
• I.e., a rate at which energy undergoes some
  process.
• E.g., being transmitted, transformed, or
  dissipated to heat.
• The question of exactly what the power/energy is
  doing is a crucial one!
• Please, please! Do not confuse this technical
  meaning of the word power with other, more
  informal uses in English!
• E.g., to mean performance
• My computer is more powerful than yours.
• ? You really mean, it has better performance.
• Or to mean energy
• How much power do we require in order to add two
  numbers?
• ? You really mean, how much energy must be
  dissipated.

4
Computational Energy Efficiency

• We define the energy efficiency ?E of a computer
  as its performance per unit of organized power
  being used up, ?E ?/Pdiss.
• Where used up means transformed into
  disorganized waste heat power that is dissipated
  out into the environment.
• Therefore, ?E (nop/t)/(Ediss/t) nop/Ediss.
• Energy efficiency is thus also the number of
  operations that can be performed per unit of
  energy that is dissipated.
• High energy efficiency is desirable because it
  can allow us to
• Compute faster while consuming power at a given
  fixed level, or
• Perform more computational work before running
  out of energy.
• Let Ediss,op denote the amount of energy
  dissipated in performing 1 standard operation.
• Note this has a reciprocal relationship with
  energy efficiency.
• That is, we have ?E (1 op)/Ediss,op and
  Ediss,op (1 op)/?E.
• Thus, high energy efficiency ?E ? low Ediss,op.

5
Trend of Min. Transistor Switching Energy
Based on ITRS 97-03 roadmaps
fJ
Node numbers(nm DRAM hp)
Practical limit for CMOS?
aJ
Naïve linear extrapolation
zJ
6
Lower Bounds on Energy Dissipation

• In todays 90 nm VLSI technology, for minimal
  operations (conventional switching of a
  minimum-sized transistor)
• Ediss,op is on the order of 1 fJ (femtojoule) ?
  ?E ? 1015 ops/sec/watt.
• Will be a bit better in coming technologies (65
  nm, maybe 45 nm)
• Conventional digital technologies are subject to
  several lower bounds on their energy dissipation
  Ediss,op for digital logic / storage /
  communication operations,
• And thus, corresponding upper bounds on their
  energy efficiency.
• Some of the known bounds include
• Leakage-based limit for high-performance
  field-effect transistors
• Roughly at least 5 aJ (attojoules) ? ?E ? 21017
  operations/sec/watt
• Reliability-based limit for all
  non-energy-recovering technologies
• Roughly 1 eV (electron-volt) ? ?E ? 61018
  operations/sec/watt
• von Neumann-Landauer (VNL) bound for all
  irreversible technologies
• Exactly kT ln 2 18 meV (on Earth) ? ?E ?
  3.51020 operations/sec/watt

7
Reliability Bound on Logic Signal Energies

• Let Esig denote the logic signal energy,
• The energy involved in storing, transmitting, or
  transforming a bits worth of digital
  information.
• But note that involved does not necessarily
  mean dissipated!
• As a result of fundamental thermodynamic
  considerations, it is required that Esig kBTsig
  ln R,
• Where kB is Boltzmanns constant, 1.3810-12 J/K
• Tsig is the temperature of the local subsystem
  carrying the signal
• R is the reliability factor, i.e., the
  improbability 1/perr of error.
• In non-energy-recovering logic technologies
  (totally dominant today)
• Basically all of the signal energy (and often
  additional energy) is dissipated to heat on each
  operation.
• In this case, minimum sustainable dissipation is
  Ediss,op ? kBTenv ln R
• Where Tenv is the temperature of the waste-heat
  reservoir
• Averages around 300 K (room temperature) in
  Earths atmosphere
• For a decent R 21017, this energy is 40 kT
  1 eV.
• For better energy efficiency, we must recover
  some of the signal energy.
• Rather than dissipating it all to heat with each
  manipulation of the signal.

8
VNL Bound on Energy Dissipation from Information
Loss
Follows directly from the reversibility of
fundamental physics!
N physical microstates per logical
macrostatebefore bit erasure(shown as 8 for
clarity in this simple example)
Physicalmicrostatetrajectories
Logical state 0,after operation
S k ln 8 3 bits
S k ln 16 4 bits
Logical state 0,before operation
?S 1 bit k ln 2
Logical state 1,before operation
Ediss ?STenv kTenv ln 2
S k ln 8 3 bits
9
Von Neumann-Landauer Bound

• Follows directly from the time-reversibility
  (invertibility) of all fundamental physical
  dynamics.
• This in turn is implied by the Hamiltonian
  formulation of mechanics and the unitarity of
  quantum mechanics. ? Very well-established.
• Implies that physical information can never be
  destroyed!
• Only reversibly transformed!
• When we lose or discard a bits worth of logical
  information,
• e.g., by erasing or destructively overwriting a
  bit storage location
• the lost information must actually remain in
  existence,
• if in no other form, then as a bits worth (k ln
  2) of physical entropy.
• Entropy simply means unknown information in the
  physical state.
• If the logical bit was originally known (not
  entropy)
• then entropy has increased in this process by ?S
  1 bit k ln 2.
• The energy in the heat reservoir must be
  increased by an amount ?STenv kTenv ln 2 in
  order to contain this additional entropy.

10
Reversible Computing

• The basic idea is simply this
• Dont erase information when performing logic /
  storage / communication operations!
• Instead, just reversibly transform it in place!
• When reversible digital operations are
  implemented using well-designed energy-recovering
  circuitry,
• This can result in energy dissipation Ediss ltlt
  Esig,
• This has already been empirically demonstrated in
  many chips.
• and even (in principle) energy dissipation Ediss
  ltlt kT ln 2!
• This is pretty clear in theory, but we are not
  yet to the point of achieving such low levels of
  dissipation experimentally.
• Achieving this goal requires very careful design,
  
• and verifying it requires very sensitive
  measurement equipment.

11
Adiabatic Circuits

• Reversible logic can be implemented today using
  fairly ordinary voltage-coded CMOS VLSI circuits.
• With a few changes to the logic-gate/circuit
  architecture.
• We avoid dissipating most of the circuit node
  energy when switching, by transferring charges in
  a nearly adiabatic (literally, without flow of
  heat) fashion.
• I.e., asymptotically thermodynamically
  reversible.
• In the limit, as various low-level technology
  parameters are scaled.
• There are many designs for purported adiabatic
  circuits in the literature,
• but, watch out! Most of designs out there
  contain fatal flaws, and are not truly adiabatic.
• Many past designers are unaware of (or
  accidentally failed to meet) all the requirements
  for true thermodynamic reversibility.

12
Reversible and/or Adiabatic VLSI Chips Designed
_at_ MIT, 1996-1999
By Frank and other then-students in the MIT
Reversible Computing group,under CS/AI lab
members Tom Knight and Norm Margolus.
13
Bistable Potential-Energy Wells
A Technology-Independent Model of Digital Devices
(Landauer 61)

• Consider any system having an (adjustable)
  potential energy surface (PES) in its
  configuration space.
• The PES should have at least two local minima (or
  wells)
• Therefore the system is bistable
• It has two stable (or at least metastable)
  configurations
• Located at well bottoms
• The two stable states form a natural bit.
• One state can represent 0, the other 1.
• This picture can also be easily generalized
  tolarger numbers of stable states.
• Consider now the PES havingtwo adjustable
  parameters
• (1) Height (energy) of the potential energy
  barrier between wells, relative to well bottoms
• (2) Relative height of the left and rightstates
  in the well (call this bias)

Potentialenergy
0
1
Generalizedconfigurationcoordinate
14
Possible Parameter Settings

• In some of the following slides, we will mention
  six qualitatively different settings of the well
  parameters, as shown below

Raised
BarrierHeight
Lowered
Left
Right
Neutral
Direction of Bias Force
15
MOSFET Implementation

• The logical state is in the location of a charge
  packet (excess of electrons) on either side
  terminal of a FET.
• The charge packet might even consist of just a
  single excess electron in a sufficiently small
  (nanoscale) logic node.
• The potential energy barrier is provided by the
  built-in voltage across the PN junctions in the
  FET.
• The barrier height is lowered when the device is
  turned on by adjusting the voltage on the gate
  electrode.
• Bias forces can be provided by (e.g.) capacitive
  coupling to nearby electrodes.

n
p
n
e?
e?
e?
16
Possible Well Transitions

• Catalog of all the possible transitions in the
  bistable wells, adiabatic not...
• We can characterize a wide variety of
  digitallogic and memory styles in terms of how
  theiroperation corresponds to subgraphs of this
  diagram.

(Ignoring superposition states.)
1states
1
1
1
leak
0
0states
0
leak
0
BarrierHeight
?E
k ln 2
?E
N
1
0
Direction of Bias Force
17
Ordinary Irreversible Logics

• Principle of operation Lower a barrier, or not,
  based on input. Series/parallel combinations of
  barriers do logic.
  Major dissipation
  in at least one of the possible transitions.

1
Input changes, barrier lowered

• Can amplify input signals.

0
Example Ordinary CMOS logics
Outputirreversiblychanged to 0
0
18
Irreversible SET/CLR operations

• Irreversible SET Turn on a pFET connecting node
  B to a high voltage source.

SET operation
Bbefore Bafter
0 0
1 1
B
B
Voltage color scheme Low / High
½CV2
B

• Irreversible CLR Turn on an nFET connecting node
  B to a low voltage source.

CLR operation
Bbefore Bafter
0 0
1 1
B
½CV2
B
B
19
Conventional Logic is Irreversible
Even a simple NOT gate, as its traditionally
implemented!

• Heres what all of todays logic gates (including
  NOT) do continually, i.e., every time their input
  changes
• They overwrite previous output with a function of
  their input.
• Performs many-to-one transformation of local
  digital state!
• ? required to dissipate ?kT on avg., by Landauer
  principle
• Incurs ½CV2 energy dissipation when the output
  changes.

Inverter transition table
Example Static CMOS Inverter
in
out
20
Example Standard CMOS Inverter
Power (Vdd)
Inputgoeshigh
Power (Vdd)
on
off
In
Out
In
Out
0
0
1
1
Barrier btwn.Out and Groundlowered,
chargefalls to lowerenergy level
off
on
Inputgoeslow
Ground (0V)
Ground (0V)
Voltage color scheme Low / High
Barrierlowered
Barrierlowered
Barrierraised
Simplified ? picture ?of PES
Charge falls in
Charge falls out
Vdd
Vdd
Out
GND
Out
GND
21
Ordinary Irreversible Memory

• (1) Lower a barrier, obliviously erasing stored
  information. (2) Apply an input bias. (3) Raise
  the barrier to latch the new informationinto
  place. (4) Remove inputbias.

(4)
Retractinput
1
1
(1) and (2) can also be in theopposite order
(4)
Dissipationhere can bemade as low as kT ln 2
Retractinput
0
Barrierup
0
(3)
Barrier up
(3)
(1)
ExamplesordinaryDRAM cell,rod logicregister
Input1
Input0
N
1
0
(2)
(2)
22
Example NMOS latch / DRAM cell

• Sequence corresponds exactly to general picture
  illustrated on previous slide.

Voltage color scheme Low / Medium / High
I
M
I
M
I
M
I
M
on
off
off
off
I
M
on
I
M
I
M
I
M
I
M
on
off
off
off
(2) Apply inputbias
(3)Raisebarrier
(1) Obliviouserasure
(4) Remove inputbias
( backto start)
Could also do these in the other order also
23
Conventional vs. Adiabatic Charging
For charging a capacitive load C through a
voltage swing V

• Conventional charging
• Constant voltage source
• Energy dissipated

• Ideal adiabatic charging
• Constant current source
• Energy dissipated

Note Adiabatic beats conventional by advantage
factor A t/2RC.
24
Adiabatic Switching with MOSFETs

• Use a voltage ramp to approximate an ideal
  current source.
• Switch conditionally,if MOSFET gate voltage Vg
  gt VVT during ramp.
• Can discharge the load later using a similar
  ramp.
• Either through the same path, or a different
  path.t RC ? t RC ?

Exact formulagiven speed fraction s ? RC/t
Athas 96, Tzartzanis 98
25
Requirements for True Adiabatic Logicin
Voltage-coded, FET-based circuits

• Avoid passing current through diodes.
• Crossing the diode drop leads to irreducible
  dissipation.
• Follow a dry switching discipline (in the relay
  lingo)
• Never turn on a transistor when VDS ? 0.
• Never turn off a transistor when IDS ? 0.
• Together these rules imply
• The logic design must be logically reversible
• There is no way to erase information under these
  rules!
• Transitions must be driven by a quasi-trapezoidal
  waveform
• It must be generated resonantly, with high Q
• Of course, leakage power must also be kept
  manageable.
• Because of this, the optimal design point will
  not necessarily use the smallest devices that can
  ever be manufactured!
• Since the smallest devices may have insoluble
  problems with leakage.

Importantbut oftenneglected!
26
Reversible Set (rSET) Clear (rCLR)

• rSET operation semantics Given assurance that a
  bit is initially 0,unconditionally change it to
  1.
• To implement Traverse the adiabat (reversible
  trajectory) shown below.
• Reverse this path to perform rCLR.

(6)
1states
1
1
Put workback in
(1)
0states
0
0
(5)
Get workout
BarrierHeight
(2)
(3)
(4)
N
1
0
Direction of Bias Force
27
rSET/rCLR transition tables

• Note that these tables are not reversible
  according to the strict traditional definition
• Since they dont represent a 1-1 transformation
  of all possible input states.
• However, if we restrict our use of these
  operations so as to always avoid the input states
  that actually result in dissipation,
• Then, we obtain a 1-1 transformation of the
  subset of the input states that are actually
  used,
• And that is the correct statement of the true
  logical requirement for avoiding Landauers
  principle!

Before rSET AfterrSET
0 1
1
Before rCLR AfterrCLR
0
1 0
28
Type 1 Input-Bias Clocked-Barrier Reversible
Latching ( Logic)

• Cycle of operation
• (1) Data input applies bias
• Add forces to do majority logic
• (2) Clock signal raises barrier
• (3) Data input bias removed

(Can amplify/restore input signalin the
barrier-raising step.)
(3)
1
1
(4)
Can reset latch reversibly (4) given copy
ofcontents.
(3)
0
0
(2)
(4)
(4)
(2)
(4)
(1)
(1)
Examples AdiabaticQCA, SCRL latch, Rod logic
latch, PQ logic,Buckled logic, Helical logic
N
1
0
(4)
(4)
29
Type 1 Example Adiabatic NMOS latch / DRAM cell

• Same as irrev. latch, just skip the erasure step!

Voltage color scheme Low / Medium / High
I
M
I
M
I
M
on
off
off
I
M
on
I
M
I
M
I
M
Can similarly use a CMOS transmissiongate
(nFET/pFET pair) to latch a full-swing signal
if necessary.
on
off
off
(1) Apply inputbias
(2)Raisebarrier
(3) Remove inputbias
(Reverse stepsto reversiblyunlatch M)
30
A Simple Reversible CMOS Latch

• Uses a single standard CMOS transmission gate
  (T-gate).
• Sequence of operation (0) input level initially
  tied to latch contents (output) (1) input
  changes gradually ? output follows closely (2)
  latch closes, charge is stored dynamically (node
  floats) (3) afterwards, the input signal can be
  removed.

Before Input Inputinput arrived removedin out
in out in out0 0 0 0 0 0 1 1 0 1
P
in
out

• Later, we can reversibly unlatch the data
  with an exactly time-reversed sequence of
  steps.

(0)
(1)
(2)
(3)
Reversible latch
31
Type 2 Input-Barrier, Clocked-Bias Reversible
Retractile Logic

• Barrier signal is amplified! Gain,
  restoring logic, fan-out.
• Must reset output prior to changing input.
• Combinational logic only!

• Cycle of operation
• (1) Inputs raise or lower barriers
• Do logic w. series/parallel barriers
• (2) Clock applies bias force, which changes
  state, or not

0
0
0
(1) Input barrier height
ExamplesHalls logic,SCRL gates,Rod logic
interlocks
N
1
0
(2) Clocked bias force applied ?
32
Type 2 example Adiabatic CMOS buffer (really,
a cSET/cCLR gate)

• Controlled-SET / controlled-CLEAR.
• Structure Essentially just a pair of CMOS
  transmission gates
• 2 transistors each, an nFET and a pFET in
  parallel
• Using dual-rail signaling, we can reversibly set
  or clear a bit on an unoccupied logic node (pair
  of voltage nodes), conditionally on an input
  node.
• Amplifies input signal.
• Fully restores logic levels.

DriveN
DriveN
InN
InN
InP
InP
on
on
DriveN
OutN
OutN
Voltage color scheme Low / High
DriveN
DriveN
InN
off
InN
InN
InP
InP
off
off
InP
OutN
OutN
OutN
(And similarly for OutP)
33
Transition Table for cSET

• It is not unconditionally reversible,
• Not a one-to-one transformation of all possible
  local states,
• But, it is conditionally reversible
• I.e., on condition that input state 1,1 is
  avoided.

Before cSET Before cSET After cSET After cSET
Source Destination Source Destination
0 0 0 0
0 1 0 1
1 0 1 1
1 1 1 0
34
Type 2 example SCRL inverter

• Same structure as static CMOS inverter, but used
  reversibly.
• Produces a fully-restored, amplified output
  signal.
• Inverters can be cascaded, but need latches to
  get feedback.

driveH
driveH
off
off
driveH
In
Out
In
Out
on
on
off
driveL
driveL
In
Out
driveH
driveH
off
on
on
In
Out
In
Out
driveL
off
off
Voltage color scheme Low / Medium / High
driveL
driveL
35
SCRL Inverter Transition Table
Before SCRL-Inv Before SCRL-Inv After SCRL-Inv After SCRL-Inv
In Out In Out
0 0
0 ½ 0 1
0 1
½ 0
½ ½
½ 1
1 0
1 ½ 1 0
1 1

• Conditionally reversible, if input is valid
  and output is ½ just before drivers do their
  thing.
• No point in even listing the table entries
  that dont occur can summarize operation
  below.

Before SCRL-Inv Before SCRL-Inv After SCRL-Inv After SCRL-Inv
In Out In Out
0 ½ 0 1
1 ½ 1 0
36
Example Adiabatic NMOS OR gate

• Input barriers along two parallel paths

A
A
Out
Out
Drive
Drive
Out A ? B
B
B
A
A

• Reverse sequence decomputes Out.
• Cant change A,B freely until then.
• With NMOS, Out is weak (orange).
• Can use an SCRL inverter to restore the
  signal levels.
• If appropriately biased
• Or, just use CMOS transmission gates
  instead (8T OR)

Out
Out
Drive
Drive
A
B
B
Out
Drive
A
A
B
Out
Out
Drive
Drive
B
B
A
A
Out
Out
Drive
Drive
B
B
37
Type 3 Input-Barrier, Clocked-Bias Latching
Logic

• ? Cycle of operation
• Input conditionally lowers barrier
• Do logic w. series/parallel barriers
• Clock applies bias force conditional bit flip
• Input removed, raising the barrier locking in
  the state-change
• Clockbias canretract

1
(4)
(4)
0
0
0
(2)
(2)
(3)
(1)
Examples Mikes4-cycle 2-level adiabaticCMOS
logic (2LAL)
(2)
(2)
N
1
0
38
2LAL 2-level Adiabatic Logic
A pipelined fully-adiabatic logic invented at UF
(Spring 2000),implementable using ordinary CMOS
transistors.
TN
T
2

• Use simplified T-gate symbol
• Basic buffer element
• cross-coupled T-gates
• need 8 transistors to buffer 1 dual-rail signal
• Only 4 timing signals ?0-3 are needed. Only 4
  ticks per cycle
• ?i rises during ticks ti (mod 4)
• ?i falls during ticks ti2 (mod 4)

?
?1
(implicitdual-railencodingeverywhere)
in
TP
out
?0
Animation
Tick
0 1 2 3
?0
?1
?2
?3
39
2LAL Cycle of Operation
Tick 0
Tick 1
Tick 2
Tick 3
?1?1
in?1
in?0
?1?0
out?1
in
?0?1
?0?0
?1?1
in0
out?0
out0
?0?1
?0?0
40
2LAL Shift Register Structure
Animation

• 1-tick delay per logic stage
• Logic pulse timing and signal propagation

?1
?2
?3
?0
in_at_0
out_at_4
?0
?1
?2
?3
0 1 2 3 ...
0 1 2 3 ...
inN
inP
41
More Complex Logic Functions

• Non-inverting multi-input Boolean functions
• One way to do inverting functions in pipelined
  logic is to use a quad-rail logic encoding
• To invert, justswap the rails!
• Zero-transistorinverters.

?0
AND gate (plus delayed A)
OR gate
A0
?
A0
B0
A1
B0
(A?B)1
(AB)1
A 0
A 1
AN
AP
AN
AP
42
Cadence simulation results

• Work by AdiaMEMS project studentsKrishna
  NatarajanVenkiteswaran Anantharam(UF ECE Dept.,
  under supervision of Dr. Frank, CISE/ECE)

43
Simulation Results from Cadence

• Assumptions caveats
• Assumes ideal trapezoidal power/clock
  waveform.
• Minimum-sized devices, 2?3? .18 µm (L)
  .24 µm (W)
• nFET data is shown pFETs data is very
  similar
• Various body biases tried Higher Vth
  suppresses leakage
• Room temperature operation.
• Interconnect parasitics have not yet been
  included.
• Activity factor (transitions per
  device-cycle) is 1 for CMOS, 0.5 for 2LAL in
  this graph.
• Hardware overhead from fully- adiabatic
  design style is not yet reflected 2
  transistor-tick hardware overhead in known
  reversible CMOS design styles

1 nJ
100 pJ
10 pJ
Standard CMOS
10 aJ
1 pJ
1 aJ
1 eV
Energy dissipated per nFET per cycle
100 fJ
2V
100 zJ
2LAL 1.8-2.0V
1V
10 fJ
10 zJ
0.5V
0.25V
1 fJ
kT ln 2
1 zJ
100 aJ
100 yJ
44
O(log n)-time carry-skip adder
With this structure, we can do a2n-bit add in
2(n1) logic levels? 4(n1) reversible ticks?
n1 clock cycles.Hardwareoverhead islt2
regularripple-carry.

• (8 bit segment shown)

3rd carry tick
2nd carry tick
4th carry tick
1st carry tick
45
32-bit Adder Simulation Results
1V CMOS
1V CMOS
0.5V CMOS
0.5V CMOS
2V 2LAL, Vsb1V
2V 2LAL, Vsb1V
(All results normalized to a throughput level of
1 add/cycle)
46
Thanks to AdiaMEMS Project Members
Left toRight Venki,Mike,Maojiao,Krishna,
Huikai
47
Plenty of room for device improvement
Power per device, vs. frequency

• Recall, irreversible device technology has at
  most 3-4 orders of magnitude of
  power-performance improvements remaining.
• And then, the firm kT ln 2 limit is encountered.
• But, a wide variety of proposed reversible device
  technologies have been analyzed by physicists.
• With theoretical power-performance up to 10-12
  orders of magnitude better than todays CMOS!
• Ultimate limits are unclear.

.18µm CMOS
.18µm 2LAL
k(300 K) ln 2
Variousreversibledevice proposals
48
A Potential Scaling Scenario for Reversible
Computing Technology

• Assume energy coefficient (energy diss. / freq.)
  of reversible technology continues declining at
  historical rate of 16 / 3 years, through 2020.
• For adiabatic CMOS, cE CV2RC C2V2R.
• This has been going as ?4 under constant-field
  scaling.
• Requires new devices after CMOS scaling stops.
• But, many potential candidates are waiting in the
  wings
• Assume affordable number of layers of active
  circuitry per chip (or per package, e.g., stacked
  dies) doubles every 3 years, through 2020.
• Competitive pressures will tend to reduce
  per-layer cost, esp. if device-size scaling
  stops, as assumed.

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Result of Scenario
40 layers, ea. w.8 billion activedevices,freq.
180 GHz,0.4 kT dissip.per device-op
e.g. 1 billion devices actively switching at3.3
GHz, 7,000 kT dissip. per device-op
Note that by 2020, there could be a factor of
20,000 difference in rawperformance per 100W
package. (E.g., a 100 overhead factor from
reversible design could be absorbed while still
showing a 200 boost in performance!)
50
Possible Cosmic (!) Implications of Reversible
Computing

• Astrophysicists Krauss and Starkman have argued
  that,
• even if we someday colonize the stars,
• The total energy we can ever harvest is finite!
• We can never reach galaxies beyond a certain
  distance,
• due to the accelerating expansion of the
  universe.
• Thus if we never create reversible computing,
• Then someday we must run out of energy! (Due to
  VNL.)
• And then, all computation (thus all life) will
  permanently cease.
• However, if we invent reversible computing,
• and if we can make it ever more energy-efficient
  over time,
• Then potentially, an infinite number of
  computations (thoughts?) can be performed using
  only a finite supply of energy!
• ? Reversible computing is needed to save the
  universe!
• If Krauss Starkmans basic arguments are
  correct.

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Infinite Computation with Finite Energy

• Suppose we perform N operations using total
  energy E,
• And we then discover how to make computation
  twice as energy-efficient.
• Then, we perform N more operations with energy
  E/2,
• and then discover how to make computation twice
  as efficient again.
• Then, do N more operations using energy E/4,
• and so on forever (you get the picture)

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Challenges that Must be Met for Reversible
Computing to Happen

• Need to design extremely efficient
  energy-recovering power-clock resonators.
• With very high quality factor Q Esig/Ediss.
• Requires very precise engineering, and very
  refined designs.
• Need to design novel logic devices with a very
  low adiabatic energy coefficient cE Edisstop.
• And develop a cost-effective manufacturing
  process for fabricating them in large numbers.
• Need to optimize reversible logic circuits,
  architectures, and algorithms.
• To minimize the overheads of reversible
  operation.
• These tasks are all quite difficult!

53
Skills that the Inventors of Future Reversible
Computers will Need

• Very strong mathematics background
• E.g., Linear (matrix) algebra, abstract algebra
  (e.g. group theory), real complex analysis,
  probability statistics.
• Very strong grasp of fundamental physics
• Mechanics, thermodynamics, electrodynamics,
  quantum mechanics, condensed matter, quantum
  chemistry, relativity
• Solid engineering knowledge skills
• Electrical engineering, solid-state devices,
  digital circuits, digital logic design,
  information communication theory, computer
  architecture, systems engineering optimization,
  software engineering, algorithm design.
• As you can see, this task is not for the faint of
  heart!
• We must seek great breadth, depth, and quality of
  knowledge,
• and close cooperation with others in large
  collaborations.

54
Conclusions

• The evolution of conventional computing
  technology is reaching a dead end
• That is, a permanent limit on its practical
  performance, due to power dissipation
  constraints.
• These limits might possibly be circumvented
• But only by aggressively moving towards new
  energy-recovering, reversible digital logic
  technologies.
• Reversible computing is physically possible,
  according to our best modern knowledge of quantum
  physics.
• But, achieving it will require extremely
  high-precision, high-quality engineering of
  nanoscale devices and systems,
• And many bright, inventive, creative people,
  working hard together.
• The future of our technology, our civilization,
  and perhaps even all life in the universe, might
  just depend on whether you and your peers choose
  to pursue the goal of meeting the reversible
  computing challenge!