Model Creation Tools for VTB and VHDLAMS

1
Model Creation Tools for VTB and VHDL-AMS

• Alan Mantooth
• July 16, 2002

Electrical Engineering Department University of
Arkansas Fayetteville, AR 72701 mantooth_at_engr.uar
k.edu http//mixedsignal.eleg.uark.edu
2
Outline

• Introduction
• Modeling approaches
• Paragon architecture
• Modeling strategy
• Paragon illustrations
• Progress update
• Conclusions Future work

3
Introduction

• Complex systems require mixed-level modeling and
  simulation for effective verification and design
  exploration
• Design exploration
• traditional system decomposition
• automated approaches involving synthesis
• Design analysis and performance verification will
  demand bottom-up approaches to behavioral model
  creation
• Analog circuit designers dont have a propensity
  to write programs, but they will use analysis
  tools

4
Modeling Approaches
5
Paragon Architecture
6
Modeling Strategy Outside-in
Enter Public Interface
7
Modeling Strategy (contd)
8
Paragon Illustrations

• Turbine model
• MOSFET
• Operational Amplifier
• Comparator

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Paragon/VTB Illustrations - Turbine
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Paragon/VTB Turbine demo

• Following the modeling strategy the turbine model
  is developed
• The VTB code is generated
• The model is compiled and loaded into a VTB
  schematic for simulation

11
Paragon Illustrations - MOSFET
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MOSFET - Topology
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MOSFET - Equations
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MOSFET curves
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MOSFET Generated Code

• library IEEE, IEEE_proposed
• use IEEE_proposed.electrical_systems.all
• use IEEE.math_real.all
• entity mosfet is
• generic (vto real 1.0 kp real 2.0e-5
  cox_prime real 3.4515e08 lambda real
  0.02 gamma real 0.0 phi real 0.6 ld
  real 0.8 l real 1.0 w real 1.0
  cgso real 35.0e-11 cgdo real 35.0e-11
  cgbo real 35.0e-11 cj real 15.0e-5 mj
  real 0.5 cjsw real 40.0e-11 mjsw
  real 0.25 pb real 0.80 fc real
  0.5 as real 15.0e-12 ad real
  15.0e-12 ps real 15.0e-12 pd real
  13.0e-12 f2 real 0.0 f3 real 0.0
  isat real 1.0e-14)
• port(terminal source, gate, drain, bulk
  electrical)
• end entity mosfet
• architecture behav of mosfet is
• quantity vGS across iGS through gate to source
• quantity vGD across iGD through gate to source
• quantity vDS across iDS through drain to source
• quantity vGB across iGB through gate to bulk 

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MOSFET Generated Code (2/5)

• quantity vBD across iBD through bulk to drain
• quantity vBS across iBS through bulk to source
• quantity vBS_leakage across iBS_leakage through
  bulk to source
• quantity vBD_leakage across iBD_leakage through
  bulk to drain
• quantity vth real quantity leff real
  quantity cgb real quantity cgs real
  quantity cgd real quantity cbs real
  quantity cbd real quantity cox real
• begin
• leff l - 2.0ld
• cox cox_primewleff
• if not vGS'above(vth - phi) use
• cgb cox cgboleff
• cgs cgsow
• cgd cgdow
• elsif ((vGS'above(vth - phi)) and (not
  vGS'above(vth))) use
• cgb cox((vth-vGS)/phi) cgboleff
• cgs (2.0/3.0)cox((vth-vGS)/phi1.0)
  cgsow
• cgd cgdow

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MOSFET Generated Code (3/5)

• elsif ((vGS'above(vth)) and (not vGS'above(vth
  vDS))) use
• cgb cgboleff
• cgs (2.0/3.0)cox cgsow
• cgd cgdow
• elsif (vGS'above(vth vDS)) use
• cgb cgboleff
• cgs cox(1.0 - ((vGS-vDS-vth)/(2.0(vGS-vth)-vD
  S))2.0) cgsow
• cgd cox(1.0 - ((vGS-vth)/(2.0(vGS-vth)-vDS))
  2.0) cgdow
• else
• cgb cgbo
• cgs cgso
• cgd cgdo
• end use
• break on vGS'above(vth - phi), vGS'above(vth),
  vGS'above(vth vDS)
• if ((not vBS'above(fcpb)) and (not
  vBD'above(fcpb))) use

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MOSFET Generated Code (4/5)

• cbs (cjas)/((1.0-vBS/pb)mj)
  (cjswps)/((1.0-vBS/pb)mjsw)
• cbd (cjad)/((1.0-vBD/pb)mj)
  (cjswpd)/((1.0-vBS/pb)mjsw)
• elsif ((vBS'above(fcpb)) and (vBD'above(fcpb)))
  use
• cbs f3((cjas)/f2 (cjswps)/f2)
  (vBS/pb)((cjasmj)/f2 (cjswpsmjsw)/f2)
• cbd f3((cjad)/f2 (cjswpd)/f2)
  (vBD/pb)((cjadmj)/f2 (cjswpdmjsw)/f2)
• else
• cbs 0.0
• cbd 0.0
• end use
• break on vBS'above(fcpb), vBD'above(fcpb)
• vth vto gamma(sqrt(phi-vBS)-sqrt(phi))
• if (not vGS'above(vth)) use
• iDS 0.0
• else

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MOSFET Generated Code (5/5)

• if (not vDS'above(vGS - vth)) use
• iDS kp(w/(l-2.0ld))(vGS-vth-vDS/2.0)vDS(1.
  0lambdavDS)
• else
• iDS (kp/2.0)(w/(l-2.0ld))((vGS-vth)2.0)(1
  .0lambdavDS)
• end use
• end use
• break on vGS'above(vth), vDS'above(vGS - vth)
• iGB cgbvGB'dot
• iGS cgsvGS'dot
• iGD cgdvGD'dot
• iBS cbsvBS'dot
• iBD cbdvBD'dot
• iBS_leakage isat(exp(0.0259vBS) - 1.0)
• iBD_leakage isat(exp(0.0259vBD) - 1.0)
• end architecture behav

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Paragon Illustration 2 Op Amp
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Op Amp Topology 1
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Op Amp Topology 2
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Op Amp Generated Code

• library IEEE, IEEE_proposed
• use IEEE_proposed.electrical_systems.all
• use IEEE.math_real.all
• entity opamp is
• generic (A real 10000.0 V_plus real
  5.0 V_minus real -5.0)
• port(terminal input1, input2, output
  electrical)
• end entity opamp
•  
• architecture ideal of opamp is
• quantity v1 across input1
• quantity v2 across input2
• quantity vout across iout through output
• begin
• vout A(v1-v2)
• end architecture ideal
•  

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Op Amp Generated Code (2/2)

• architecture limited of opamp is
• quantity v1 across input1
• quantity v2 across input2
• quantity vout across iout through output
• quantity vdiff real
• begin
• vdiff v1-v2
• if (vdiff'above(V_plus)) use
• vout V_plus
• elsif (not vdiff'above(V_minus)) use
• vout V_minus
• else
• vout Avdiff
• end use
• break on vdiff'above(V_plus),vdiff'above(V_minus)
  
• end architecture limited

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Paragon Illustration 3 - Comparator
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Comparator Topology
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State Machine
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Comparator Generated Code

• library IEEE
• library IEEE_proposed
• use IEEE_proposed.electrical_systems.all
• use IEEE.math_real.all
• entity comparator is
• generic (low real 1.0 high real 3.0
  timeout time 1.0 ns)
• port(terminal input1, input2 electrical signal
  output out std_ulogic)
• end entity comparator
• architecture hysteresis of comparator is
• type states is (unknown, zero ,one, unstable)
• quantity v across input1 to input2
• function compare(v_in,low,high real) return
  states is
• begin
• if (v_in lt low) then
• return zero
• elsif (v_in gt high) then

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Comparator Generated Code (2/3)

• return one
• else
• return unknown
• end if
• end function compare
• begin
• process
• variable state states compare(real(v), low,
  high)
• begin
• case state is
• when one gt
• output lt '1'
• wait on v'above(high) -- wait for change
• state unstable
• when zero gt
• output lt '0'

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Comparator Generated Code (3/3)

• wait on v'above(low)
• state unstable
• when unknown gt
• output lt 'X'
• wait on v'above(high), v'above(low)
• state compare(real(v), low, high)
• when unstable gt
• wait on v'above(high), v'above(low) for timeout
• state compare(real(v), low, high)
• end case
• end process
• end architecture hysteresis

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Progress Update
VTB Semantics
Database Extensions
Tools
Code Generation
Test and Debug
50
75
100
0
10
Percent Complete
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Conclusions Future Work

• Paragon allows designers to create behavioral
  models in a top-down, language-independent
  fashion
• The models can be generated in a number of
  hardware description language formats
• Paragon is an extensible environment that will
  accommodate bottom-up methods as well
• Model testing and validation are integral to the
  process
• Further extensions in mixed-signal
• Adding bottom-up methods currently in research

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Acknowledgements

• Anthony Austin, BSCmpE student
• Vivek Chaudhary, MSEE student
• Matt Francis, BSEE student
• Pinki Mallick, MSEE student
• Jianhua Mao, MSEE student
• Eddie Pettis, BSEE student
• Wei Zheng, Ph.D. student
• Financial support of USC/ONR
• Roger Dougal, Antonello Monti, Eugene Solodovnik