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Presentation kit

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... by the times of DRAM Row Addr. Change. Efficient DRAM Access - Recursive ... SATA, WSG, PRML, Analog Front-End Integration. 0.18 m CMOS with 27.5 mm2 die size ... – PowerPoint PPT presentation

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Title: Presentation kit


1
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2
A CMOS SoC for 56/18/16 CD/DVD-dual/RAM
Applications (ISSCC2006 paper 14.8)
  • Speaker Bing-Yu Hsieh
  • MediaTek Inc.,
  • Hsin-Chu, Taiwan
  • Authors
  • Jyh-Shin Pan, Hao-Cheng Chen, Bing-Yu Hsieh,
    Hong-Ching Chen, Roger Lee, Ching-Ho Chu,
    Yuan-Chin Liu, Chuan Liu, Lily Huang, Chang-Long
    Wu, Meng-Hsueh Lin, Chun-Yiu Lin, Shang-Nien
    Tsai, Jenn-Ning Yang, Chang-Po Ma, Yung Cheng,
    Shu-Hung Chou, Hsiu-Chen Peng, Peng-Chuan Huang,
    Benjamin Chiu, Alex Ho

3
Outline
  • Overview
  • System Architecture
  • Solutions for Low Power Issue
  • Performance Comparison
  • Summary

4
Overview
  • Highly Integrated Commercial Application
  • Integrated Analog Front-End
  • Built-in 1.5Gb/s SATA PHY
  • On-Chip Write Strategy Generator
  • PRML Read Channel
  • Low Power Control
  • Supports Multiple Format of Discs
  • CD/DVD-dual/DVD-RAM Record/Playback Operation
    Speed up to 56xS/18xS/16xS

5
System Architecture of FMSOC
Spindle
Pick-up
6
Solutions for Low Power Issue
Optimization Efficiency
ARCHITECTURE
  • Efficient DRAM Access
  • Adaptive Clock Control
  • Multiple Clock Design
  • Clock Suppression and Gating
  • Voltage Partition
  • Reduce Clock Buffer

RTL
BACK-END
7
Efficient DRAM Access - Bandwidth
  • Large DRAM B.W. Requirement
  • DRAM is shared to multiple functions
  • DRAM Access Efficiency
  • Performance Index Ave. cycle to access each
    word
  • Dominated by the times of DRAM Row Addr. Change

8
Efficient DRAM Access - Recursive Encode
9
Adaptive Clock Control - Background
  • Data Rate of Optical Storage Varies with
  • Rotation Speed
  • Radius of the Access Point
  • Numerical Controlled Oscillator
  • Adaptive Control with Linear Steps

10
Adaptive Clock Control - Architecture
Automatically adjust system clock with linear
increments according to a throughput rate
indicator
11
Adaptive Clock Control - Performance
.
q
Fixed Freq.
73MHz
e
r
67MHz
70
(94.4mA)
F
)

z
k
(90.1mA)
H
60
56MHz
c
o
M
l
Adaptive

50
(81.5mA)
C

(Digital Core Current)
t
42MHz

i
Freq.
n
m
40
u
e
(70.4mA)
(
t
s
30
y
S
9.2
12.5
16
15.3
DVD Read Speed (unit xS)
12
Chip Micrograph
13
Chip Specification
14
Comparisons of the Chip Performance
15
Summary
  • Performance
  • Single Chip SoC with CD/DVD-dual/RAM Operation
    Speed up to 56xS/18xS/16xS
  • Integration
  • SATA, WSG, PRML, Analog Front-End Integration
  • 0.18 ?m CMOS with 27.5 mm2 die size
  • 772mW _at_ 16xS DVD playback
  • Architectural Optimization for Low Power
  • Recursive Parity Encode
  • Adaptive Clock Control
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