A Guide to PC Hardware Maintenance and Repair

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Chapter 8 Searching Your Memory
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Objectives

• To learn how memory works
• To learn how the system locates data in memory
• To develop an understanding of factors that
  affect the installation of memory

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The Memory Controller Circuit

• Originally a separate chip on the motherboard
  called the Memory Control Chip. Either way, its
  still the MCC.
• Controls where data is stored
• Controls the refresh cycle

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Memory Chip Design

• Each bit of data in a DRAM chip is a single
  transistor coupled with a single capacitor.
• DRAM chips are laid out like a spreadsheet, with
  rows and columns of bits.
• If a capacitor is charge, the transistor is open,
  rendering a 1.
• If a capacitor is not charged, it is closed,
  rendering a 0.

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A DRAM Chip is laid out like a spreadsheet, with
rows and columns of transistors that store the
bits of data.
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Refreshing RAM

• Is not like a refreshing beverage.
• Each capacitor in a DRAM chip loses its charge in
  a short amount of time.
• The refresh cycle comes along and adds a fresh
  charge to each capacitor with more than 50
  charge. Capacitors with under 50 are not
  refreshed.

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Refresh Rate

• Is NOT based on time.
• Refresh rate is based on the number of columns of
  memory cells that are charged in each refresh
  cycle.
• A 4K rate means that 4000 columns are charged at
  a time.

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Microcircuits of the MCC

• Row Access Strobe (RAS)
• is used to locate the specific row in which a bit
  cell is located.
• Column Access Strobe (CAS)
• is used to locate the specific column in which a
  bit cell resides.

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A Memory I/O Operation

• The chipset doesnt find the data the CPU needs
  in cache, so it requests a search of RAM.
• The MCC determines the data is present in RAM.
• The first step is a pre-refresh. All cells get a
  new refresh, even if they just had one.

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Memory I/O Operations (cont.)

• RAS then locates the correct row
• A short delay (RAS/CAS delay or CAS Latency)
  occurs while RAS turns the I/O over to CAS
• CAS locates the correct column
• Data moves from RAM to cache

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Memory Types

• Fast Page Mode (FPM)
• Early DRAM required a new MCC command cycle and a
  complete I/O operation for every memory read,
  even if the next byte of data was directly
  adjacent to the last byte read.
• With FPM a new RAS operation was not required if
  the data was in the same column.

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Memory Types (cont.)

• Extended Data Out (EDO)
• Works along the same lines as FPM
• Can line up a new I/O operation on the same clock
  cycle as data is being transferred out.

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Memory Types (cont.)

• Synchronous DRAM (SDRAM)
• Moved some of the MCC circuitry onto the memory
  module
• Now the CPU talks directly to the memory module
• A memory read can occur on each clock cycle of
  the front side bus

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Memory Types (cont.)

• Double Data Rate RAM (DDR)
• Works just like SDRAM
• Moves two bits of data from each bit on every
  clock cycle
• Effectively doubles the speed

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Memory Types (cont.)

• Virtual Channel SDRAM (VCSDRAM)
• Works like SDRAM
• Can be configured to deliver data across as many
  as 16 separate channels
• Allows up to 16 threads to be running on multiple
  CPUs at one time without RAM becoming a bottleneck

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Memory Packages

• DIPP
• SIPP
• SIMM
• DIMM
• RDIMM

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The DIPP

• No, it is not your younger brother
• Dual In-line Pin Package
• Provides a single bit of data per clock cycle
• Looks like a high-tech spider

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The SIPP

• Single In-line Pin Package
• Placed multiple DRAM chips on a single module
  that mounted with a single row of pins

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Single In-line Memory Module

• First memory module to use an edge card connector
• Available in 30-pin and 72-pin versions
• 72-pin version, notched off center to prevent
  reverse mounting.

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Dual In-line Memory Module

• Connectors on opposite side of edge card perform
  different functions
• 168 and 184-pin versions
• Two notches in edge card

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Rambus In-line Memory Module

• Specific to Rambus Memory
• 184-pin DIMM with only a single notch
• All Rambus sockets MUST be filled, either with
  memory or a continuity module

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Small Outline DIMM

• Used for Notebooks and some video cards
• First generation SO-DIMM was 72-pin
• Later versions are all 144-pin

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Memory Banks

• All memory modules have a measurable bit width
• How many bits of data transfer on a single
  movement of data over the bus
• CPUs have a bit width
• Memory bank bit width must equal CPU bit width

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Memory Modules and Bit Width

• DIPP ? 1 bit
• SIPP ? 8 bits
• 30-pin SIMM ? 8 bits
• 72-pin SIMM ? 32 bits
• DIMM ? 64 bits

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CPUs and Bit Width

• First Generation ? 8 bits
• Second Generation ? 16 bits
• Third/Fourth Generation ? 32 bits
• Fifth Generation and up ? 64 bits

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Error Detection/Correction Methods

• Parity
• A 9th bit placed in each byte to indicate an even
  or an odd number of 1s in byte.
• If parity check failed, system locked up.
• Error Correction Code
• The number of 1s in data package is stored in
  4-32 bits. If number doesnt match, data is sent
  again.

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Troubleshooting Memory

• Memory not detected
• Memory quantity mismatch
• Memory read errors
• General Protection Faults