Digital Baseband

1
Digital Baseband

• M. Josie Ammer
• BWRC retreat 6/1/2000

2
Introduction

• Physical Layer (PHY) Design Flow - digital
• Two-Chip Intercom (TCI) PHY Specification
• Receiver Timing Recovery Algorithm
• Receiver Implementation Complexity
• State Machine Translation to Hardware
• Power Estimation
• TCI PHY Future
• Plans for PicoRadio PHY

3
Physical Layer Design Flow
4
TCI Physical Layer

• TCI Application Intercom-style voice
  conversations
• 15-20 users, 64Kb/s/user
• Requires up and downlink, peer-to-peer PHY
• Provide simple interface to protocol stack

• Existing RF, analog components support
• 31 chips/symbol DSSS
• 25 MHz chip rate
• QPSK mod
• Supports 1.6Mb/s
• TDMA supports required bandwidth, user count

• Leverage existing analog, RF components for TCI

5
Receiver Algorithm

• 8x over-sampled A/D supplies 8 streams of 9-bit
  data (noise is correlated amongst streams)
• Choose 3 of the 8 streams (Coarse Timing/Pilot
  Detect)(Search for peaks of certain amplitude in
  matched filter)
• Choose final stream (Fine Timing)
• Estimate and correct carrier offset
• Use training symbols to achieve coherent lock
  (DPLL)
• Maintain coherent lock during data mode (DPLL)

6
Receiver Complexity
State Flow and Data Flow Transistor
counts(approximate)
State Flow Diagram Complexity
7
Stateflow Compilation Example
Example PLL control Stateflow chart
Simple State Machine- 5 states- 4 inputs
(1-bit)- 5 outputs (1-bit)- No temporary
variables- No assignment and usage within one
state

• For simple state machines, compiler is efficient!

8
SF2VHD Status

• Default transition, initialization not
  implemented properly (to be fixed soon)
• Evaluate SF2VHD efficiency on complicated state
  machines
• Energy estimates without going through synthesis?

9
Power Estimation

• Previously, only able to get transistor counts
• Current work (Ning)
• Characterize module energy
• Log activity for block inputs during Simulink
  simulation
• Combine activity with energy characterization
• Get more accurate power estimation
• Also working on timing and area estimation

10
Power Estimation Example
Log file output foo.cpe_stage3.Add_Sub 10 foo.c
pe_stage3.MUX1 1 foo.Reg_C1.Reg1 11 foo.cpe_stage1
.Add_Sub 10 foo.cpe_stage7.Add_Sub1 8 foo.cpe_stag
e7.Add_Sub 8 foo.cpe_stage6.Add_Sub1 9 foo.cpe_sta
ge6.Mult 9 foo.cpe_stage5.MUX3 3 foo.cpe_stage5.MU
X2 2 foo.cpe_stage5.MUX1 3 foo.cpe_stage5.MUX 3 fo
o.cpe_stage1.Add_Sub1 10
Simulink simulation (fixed pt.)
Use activity information to get better power
estimates.
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TCI PHY Future Tasks
Gross Power Estimates

• Provide feedback to SF2VHD team in order to
  complete tool
• Use new in-house power estimate tool to
  analyze/optimize power
• Work with ICMake team to produce PHY digital core
• Integrate PHY core with protocol stack core
  (being developed in parallel)

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Future Plans for Pico Radio

• Select, implement lowest power radio architecture
  
• CDMA, OFDM, neither
• Direct conversion, Low-IF
• Lower bit rate
• In cooperation with analog and RF design groups
• Develop low power carrier detect and coarse
  timing
• Reduced bit width, oversampling
• 2-bit ADC at 2x oversample(feasibility
  demonstrated in 98)

Goal 60uW for entire PicoRadio Physical Layer!
(1 duty cycle)
13
Links to other work

• IC Make design flow
• SF2VHD
• Module generators
• Clock methodology
• Power estimation from Simulink
• Physical Layer for PicoRadio
• Protocol design and verification
• Protocol implementation
• Tool chain (software and hardware)
• Architectures and circuits
• Analog and RF group

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Abstract

• Timing recovery circuitry accounts for more than
  half the power of the TCI receiver.
• This poster describes
• Digital timing recovery algorithm for TCI
• Hardware implementation approach
• Improvements to make for PicoRadio

PicoRadio requires 100x improvement over TCI!