Reprogrammable Control Circuits

1
Reprogrammable Control Circuits (Specification,
Modeling, Synthesis and Implementation)
Valeri Skliarov
Provas de agregação, 27 e 28 de Junho de 2001
Universidade de Aveiro
2
Outline

• Control Circuits (Functions and Scope)
• Hardware and Software Implementation
• Programmable Logic Devices
• Design Flow and Design Steps
• Integrated View to the Proposed Methodology
  (Specification, Modeling, Methods, Template-Based
  Synthesis, Computer-Aided Design Technique)
• Practical Applications
• Conclusion

3
Functions
Control Device
Modularity Hierarchy Parallelism Recursivity Virtu
alability etc.
Synthesis
External world
4
Outline

• Control Devices (Functions and Scope)
• Hardware and Software Implementation
• Programmable Logic Devices
• Design Flow and Design Steps
• Integrated View to the Proposed Methodology
  (Specification, Modeling, Methods, Template-Based
  Synthesis, Computer-Aided Design Technique)
• Practical Applications
• Conclusion

5
Scope
Control Device
6
Control Device
7
Outline

• Control Devices (Functions and Scope)
• Hardware and Software Implementation
• Programmable Logic Devices
• Design Flow and Design Steps
• Integrated View to the Proposed Methodology
  (Specification, Modeling, Methods, Template-Based
  Synthesis, Computer-Aided Design Technique)
• Practical Applications
• Conclusion

8

• Fast
• Optimized for particular applications
• Optimized for size
• etc.

• Flexible
• Customizable
• Cheap
• etc.

• Very expensive
• Long development time
• Unique and it cannot be reused in general case
• etc.

• Slowly
• Non optimized for applications
• Has significant delay when handles events in
  reactive systems
• etc.

9
Outline

• Control Devices (Functions and Scope)
• Hardware and Software Implementation
• Programmable Logic Devices
• Design Flow and Design Steps
• Integrated View to the Proposed Methodology
  (Specification, Modeling, Methods, Template-Based
  Synthesis, Computer-Aided Design Technique)
• Practical Applications
• Conclusion

10
ADM-XRC
XC4000
PLD
Virtex XCV812E
280 Blocks (4096 Bits each)
16x1 bit synchronous RAM
16x2 bit or 32x1 bit or 16x1 bit
dual-port synchronous RAM
CLB Array 5684 4704 elements Logic
Cells 21 168 BlockRAM Bits (250 MHz) 1
146 880 Distributed RAM Bits 301 056 User
I/O 556 Synchronous system clock
rates up to 240 MHz
Totally 1 146 880 Bits
40961 ............ 25615
11
Dynamically Reconfigurable Systems
RAM
RAM
RAM
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Control Devices
13
Outline

• Control Devices (Functions and Scope)
• Hardware and Software Implementation
• Programmable Logic Devices
• Design Flow and Design Steps
• Integrated View to the Proposed Methodology
  (Specification, Modeling, Methods, Template-Based
  Synthesis, Computer-Aided Design Technique)
• Practical Applications
• Conclusion

14
Design Flow
15
State of the Art
Specification
etc.
16
GSA
LSA
MSA
Samary Baranov Logic Synthesis for Control
Automata. Kluwer, 1994, 392 p. (pp. 86-91)
17
(No Transcript)
18
State of the Art
Design of Reprogrammable Digital Systems
RENCO, Firefly. BioWatch (IEEE Trans. on Comp,
Vol.48, N6, June, 1999), CHIMAERA (ISCA2000),
MorphoSys (Circuits and Systems, 1999, Vol.10, N
1), GARP (http//brass.cs.berkeley.edu/garp.html),
PRISC, OneChip, REMARC, NAPA, etc (CS294-6
Reconfigurable Computing)
From the strategic point of view most of the
relevant work on the design of reprogrammable
(reconfigurable) systems is in the area of
virtual problem-specific circuits that offer a
mixture of hardware performance and software
versatility.
P. M. Athands, H. F. Silverman, Processor
Reconfiguration trough Instruction Set
Metamorphosis, Computer, vol. 26, nº 3, 1993.
PRISM
M. Gokhale et al, Building and Using a
Highly-Parallel Programmable Logic Array,
Computer, vol. 24, nº 1, pp. 81-89, January 1991.
Splash
C. Iseli, E. Sanchez, Spyder a Reconfigurable
VLIW Processor Using FPGAs, Proc. of the IEEE
Workshop on FPGAs for Custom Computing Machines,
1993.
Spyder
Jean E.Vuillemin, et al, Programmable Active
Memories Reconfigurable Systems Come of Age,
IEEE Trans. On VLSI Syst., vol. 4, no. 1, 1996.
PAM, etc.
19
State of the Art
G. Brebner. Field-Programmable Logic Catalyst
for New Computing Paradigms. FPL'98, Springer,
1998, pp. 49-58.
Run-time modifications are considered to be an
attractive way of allowing efficiency in circuit
size
Various techniques for run-time
reconfiguration have been proposed
N. Shirazi, W. Luk, P.Y.K. Cheung.
Run-Time Management of Dynamically
Reconfigurable Designs. FPL'98, Springer, 1998,
pp. 59-68.
In the main they assume dynamic swapping of
replaceable blocks. These operations can be
controlled by finite state machines.
J. Rabaey. Silicon Platforms for the
Next Generation Wireless Systems - What Role
Does Reconfigurable Hardware Play? Proceeding
of FPL'2000, Villach, Austria, 2000, pp.277-285.
Useful practical applications of dynamically
modifiable control devices were discussed in ?
I.Skliarova,A.Ferrari. Exploiting FPGA-Based
Architectures and Design Tools for Problems of
Combinatorial Computations. Proceeding of
SBCCI'2000, Manaus, Brazil, 2000.
20
State of the Art
Synthesis of Control Circuits
21
State of the Art
Synthesis of Control Circuits
22
Outline

• Control Devices (Functions and Scope)
• Hardware and Software Implementation
• Programmable Logic Devices
• Design Flow and Design Steps
• Integrated View to the Proposed Methodology
  (Specification, Modeling, Methods, Template-Based
  Synthesis, Computer-Aided Design Technique)
• Practical Applications
• Conclusion

23
Concurrent branching
Hierarchy
Parallelism
Merging
Alternative branching
Virtualability
Specification
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Specification methods
Specification
25
Specification and synthesis of HFSM
State encoding, Synthesis of CC, etc
G1,
G2,
G3,...
a(t1) ?( a(t),X(t),z(t),?(t),zprev,?prev
) Y(t) ?( a(t),X(t) ) Y(t) ?( a(t) ).
Modeling
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a0
a2
a6
a9
a3
a7
a10
a8
a11
a4
a5
a1
a1
a0
Methods
27
stack decrement
Methods
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Specification and synthesis of PHFSM

• Based on hierarchical implementation of
  control circuit.
• Based on partial state encoding technique.
• Based on communicating finite state machines.
• Based on one-hot implementation for parallel
  algorithms.
• Based on Extended HGSs (EHGS) that provide
  mechanisms
• for synchronization and permit
  implementation based on
• communicating modules that implement
  components of HGSs.

R-M-V
M-V
It is supported by method of synthesis of modules
with dynamically modifiable functionality
V.Sklyarov. Graphical Description and Hardware
Implementation of Parallel Control Algorithms.
Proceedings of PDPTA'99, June, Las Vegas, USA,
1999, pp. 1390-1396.
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Specification
30
Synthesis of template-based FSMs
RAM
RAM
RAM
Template-Based Synthesis
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Synthesis of RAM-based FSMs
2RL(RN) bits 224 bits.
Template-Based Synthesis
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K(am1) 01P3P4
K(am2) 1P2P31
RAM address
Template-Based Synthesis
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4 times
2RL(RN) bits 224 bits.
2RL(RN) bits 56 bits.
Template-Based Synthesis
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y1,...,y4
The size is 56 bits
Template-Based Synthesis
35
x1
x8
afrom
P(afrom,ato) ?(afrom,X (afrom,ato) )
P1
P2
P3
P1a1x1?a2x6?a5x6 P2a1x2?a2x7?a5x4 P3a1x3?a2x8
?a5x5.
Replacement of Input Variables
P2a5(?4?x5), P3 a5 x4(x5?x6)?a2(?7?x6x8)?
a1x1?2x3, P4a1x1x2?a2x7x8.
Template-Based Synthesis
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x1
x9
afrom
P(afrom,ato) ?(afrom,X (afrom,ato) )
Cms
P1
P2
P3
P4
P1a2 (x5?6 ? ? 5x6) a2(x5?x6) P2a1?3x4 ? a6x8
? a7x9 P3a0?1 ? a1?3?4 ? a5?7 P4a0(x1? ? 2) ?
a2?5.
Template-Based Synthesis
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Template-Based Synthesis
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1. The codes for different FSM states must be
orthogonal
2. Functional dependency of outputs (that form
vectors Cms) on inputs (x1,...,xL ? P1,...,PG)
has to be minimized
01P3P4
Template-Based Synthesis
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Cms
(cms a cef) ? (m e) (cms b cef) ? (s f).
Template-Based Synthesis
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Combinatorial problems

• splitting transitions
• a set of encoding methods
• mapping hypergraphs onto encoding tables
• compression of graphs based on specified
  constraints
• optimization based on encoding tables, etc.
• decomposition based on relationships
  specified on finite sets of Boolean
  variables
• sequential graph coloring, etc.

Methods
V. Sklyarov Synthesis of Finite State Machines
Based on Matrix LSI. Minsk, Science and
Techniques, 1984, 206 p.
41
Methods
V.Sklyarov Synthesis of Microprogramming Automata
on the Base of Standard PLAs. Automatics and
Computers, 1982, N 4, pp. 28-35.
42
CC1
CC2
Methods
(am ? as) A(am) ? A(as) ? ?
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20 states
XXXXX
XX 0 0 1
a1a3a12a20
Methods
V. Sklyarov Applying FSM Theory and OOP to the
Logical Synthesis of Control Devices. ET, 1996,
Vol. 1, N 6, pp. 515-529.
44
Optimization based on the model of interaction
"control unit - datapath"
Datapath
Control Unit
Methods
45
Methods
46
x1 x2 x3 x4
a2 a3 a4 a5
Methods
V. Sklyarov The Tables of Logic Conditions and
Their Use for Synthesis of Control Automata.
Automatics and Computers, 1980, N 3, pp. 36-41.
47
Methods
x1 x2 x3 x4
a2 a3 a4 a5
X1 X2 X3 X4
Xi ? Xj ? eij eji ? -
V.Sklyarov Minimization of the Number of
Microoperations and Logic Conditions in
Microprogram. Automatics and Telemechanics, 1980,
N 9, pp. 157-164
48
Yj ort Yk ? I(Yj) ? I(Yk) ? Yj ins Yk ?
I(Yj) ? I(Yk) ? ?
y1 y2 y3
Y1 Y2 Y3
Y
Methods
y1 and y2 ? y1-2
V.Sklyarov Minimization of the Number of
Microoperations and Logic Conditions in
Microprogram. Automatics and Telemechanics, 1980,
N 9, pp. 157-164
49
Modeling
Modeling
Educational purposes
V.Sklyarov Hardware/Software Modelling of
FPGA-based Systems. Parallel Algorithms and
Applications, will be published in 2001, pp. 1-21.
50
Modeling
V.Silva, F.Santos, V.Sklyarov. A interligação do
Visual C com as FPGAs da XILINX. Electrónica e
Telecomunicações, Jan., Vol. 2, Nº7, 2000, pp.
874-883
51
Computer-aided design technique
1. System for automatic synthesis of
microprogramming control devices (Minsk-32, EC -
FORTRAN IV) - 1980. Commercial System supported
by enterprise standard.
2. Complex of Tools for Computer-Aided Design of
Logic Control Devices on the Base of Programming
LSIs with Matrix Structure (EC, PC - PL1,
PASCAL, C) - 1992. The system was used in a
number of Universities and industrial
enterprises.
3. Integrated Development Environment for Logic
Synthesis Based on Dynamically Reconfigurable
FPGAs. (PC - C) - 1998.
4. Methods and tools for Logic Synthesis of
Digital Devices based on FPGA (PC - C).
Computer-Aided Design Technique
52
Computer-Aided Design Technique
K.Kondratjuk
53
Remark this picture was taken from presentation
of A.Melo
Computer-Aided Design Technique
54
Outline

• Control Devices (Functions and Scope)
• Hardware and Software Implementation
• Programmable Logic Devices
• Design Flow and Design Steps
• Integrated View to the Proposed Methodology
  (Specification, Modeling, Methods, Template-Based
  Synthesis, Computer-Aided Design Technique)
• Practical Applications
• Conclusion

55
1978
1984
Project 67-82 with enterprise KBTM Methods of
Automatic Design of Digital Systems for the
Control of Technological Processes for Assembling
of Microchips (on the base of Programming Logic
Devices)
Output The following controllers were designed
and fabricated KZR-1, ZRU-100, EM-3062, EM-4060
56
Practical Examples
Algorithm Brian W.Kernighan, Dennis M.Ritchie,
The C Programming Language, Prentice Hall, 1988.
57
V.Sklyarov. Hierarchical Finite-State Machines
and Their Use for Digital Control. IEEE Trans.
on VLSI Systems, 1999, Vol. 7, No 2 (p. 226).
58
Combinatorial Processor
Unique repeated operations
Examples 1. Covering. 2. Satisfiability, etc.
A.Zakrevskij Combinatorial Problems over Logical
matrices in Logic Design and Artificial
Intelligence. ET, 1998, N2.
Remark this picture was taken from presentation
mentioned below
I.Skliarova, A.Ferrari Synthesis of
Reprogrammable Control Unit for Combinatorial
Processor, Proceeding of IEEE DDECS, Gyor, 2001,
pp. 179-186.
59
Outline

• Control Devices (Functions and Scope)
• Hardware and Software Implementation
• Programmable Logic Devices
• Design Flow and Design Steps
• Integrated View to the Proposed Methodology
  (Specification, Modeling, Methods, Template-Based
  Synthesis, Computer-Aided Design Technique)
• Practical Applications
• Conclusion

60
Conclusion
1. The lecture presents the design problem for
Reprogrammable Control Circuits and summarizes
theoretical and practical results of the
author that have been received during more than
25 years.
2. The primary output of the research activity
can be shown through the following novel methods
and tools that have been proposed and exploited

• Graphical modular specification and
  optimization based on
• Hierarchical Graph Schemes and their
  extensions

• A set of models, such as HFSMs, PHFSMs,
  RAM-based FSM,
• etc. It is very important that these models
  provide direct support for
• the design of reconfigurable digital systems

• Template-based synthesis

• Design methodology allowing to synthesize
  reconfigurable control
• devices from the proposed specification. This
  methodology
• encapsulates combinatorial models, methods of
  digital
• synthesis and computer-aided design tools.

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Future Work
will be devoted to problems that exist in the
considered scope. They are the following
1. Specification, verification, optimization,
synthesis and implementation of parallel logic
control devices.
2. Design of application-specific reconfigurable
systems.
3. Exploiting new combinatorial methods, models
and computer- aided design tools for synthesis
of reconfigurable systems.
4. Application-specific reconfigurable
systems-on-chip
5. Testing of reconfigurable systems.