EET 3350 Digital Systems Design

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EET 3350Digital Systems Design
Introduction to VHDL An Overview

• Dan Solarek

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What is VHDL?

• VHDL
• VHSIC Hardware Description Language
• where VHSIC
• Very High Speed Integrated Circuit
• A technology independent, standard language for
• hardware description
• simulation
• synthesis

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What is VHDL?

• VHDL is a programming language that has been
  designed and optimized for describing the
  behavior of digital systems.
• Syntax is similar to C (actually, more like Ada)
• It is highly typed
• includes a rich set of data types
• Allows concurrent processing
• Not a general purpose programming language

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History of VHDL Development

• Outgrowth of the DARPA VHSIC Program
• Vendors designing large chips needed to exchange
  data describing their designs
• IBM, Texas Instruments, and Intermetrics got the
  contract in 1983 and released VHDL 7.2 in 1985
• Released to the IEEE for standardization in 1986
• Became IEEE Std 1076-1987
• Reballoted/upgraded to IEEE Std 1076-1993
• Released IEEE Std 1164-1993, STD_LOGIC_1164
• 9-valued logic definition, math functions for
  std_logic

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Why VHDL?

• It is a Standard
• Data Exchange medium between Vendors
• Communications medium between CAD Tools
• Not Proprietary
• Promotes interoperability and design re-use
• Not technology-specific
• Human-Readable
• Can be used to describe the behavior of a design,
  or to synthesize the design itself
• Supports a wide range of abstraction levels
• Can model a system, board, chip,
  register-transfer-level (RTL), or gate level
  designs

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VHDL Features

• Supports Hierarchy
• Flexible design methodology Top-down, bottom-up,
  or both
• Has elements to make large-scale design easier
• e.g., components, functions, procedures,
  packages, configuration
• Supports three types of modeling styles
• Behavioral (sequential statement model like a
  program)
• Dataflow (concurrent statement modeling)
• Structural (for connecting components)
• Test Benches can be written in the same language
• circuits can be verified by simulation before
  synthesis
• Propagation delays, min-max delays, setup and
  hold timing, timing constraints, etc. can all be
  described naturally

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Basic Hardware Design Flow
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VHDL Design Flow

• 1. Hierarchical / block diagram
• Figuring out the basic approach and building
  blocks at the block-diagram level.
• Large logic designs are usually hierarchical, and
  VHDL gives you a good framework for defining
  modules and their interfaces and filling in the
  details later.
• 2. Coding
• Actual writing of VHDL code for modules, their
  interfaces, and their internal details.

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Design Flow

• 3. Compilation
• Analyses your code for syntax errors and checks
  it for compatibility with other modules on which
  it relies.
• Compilation also creates the internal information
  that is needed for simulation.
• 4. Simulation
• A VHDL simulator allows you to define and apply
  inputs to your design, and to observe its
  outputs.
• Simulation is part of a larger step called
  verification. A functional verification is
  performed to verify that the circuits logical
  operation works as desired independent of timing
  considerations and gate delays.

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Design Flow

• 5. Synthesis
• Converting the VHDL description into a set of
  primitives or components that can be assembled in
  the target technology.
• For example, with PLDs or CPLDs, the synthesis
  tool may generate two-level sum-of products
  equations. With ASICs, it may generate a netlist
  that specifies how the gates should be
  interconnected.
• 6. Fitting / Placement Routing
• Maps the synthesized components onto physical
  devices.

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Design Flow

• 7. Timing verification
• At this stage, the actual circuit delays due to
  wire lengths, electrical loading, and other
  factors are known, so precise timing simulation
  can be performed.
• Study the circuits operation including
  estimated delays, and verify that the setup,
  hold, and other timing requirements for
  sequential devices (like flip-flops) are met.

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Elements of VHDL

• Syntax (the rules)
• Five design units (or elements)
• Identifiers (naming constraints)
• Data objects (what you name)
• Data types (enumerated, integer, arrays, etc.)
• Examples

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VHDL Provides Five Design Units

• Entity Declaration
• Specifies the NAME and lists the interface PORTS
• Architecture Body
• Models the actual circuit guts within an entity
• Configuration Declaration
• Identifies which arch. should be used with an
  entity
• Specifies location of components used within
  arch.
• Package Declaration like a header file in C
• Package Body like an implementation file in C
• Packages are libraries containing type
  definitions, overloaded operators, components,
  functions, and procedures. They have a
  declarative section and a BODY section.
  Elements of a Package can be used by many
  entities in a design, or many designs.

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VHDL Identifiers (Names)

• Basic identifier
• starts with a letter
• made up of letters, numbers, and underscore _
  character
• cannot end with an underscore
• case-insensitive MY_Signal_Name
  my_signal_name
• Extended Identifier
• any text within 2 backslashes
• e.g., \2FOR\ \-23signal\ etc.
• case is significant \COUNT\ not equal to
  \count\, and\FRAMUS\ not equal to basic
  identifier FRAMUS
• Not often used not necessarily supported in
  synthesis !!

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Four Classes of Data Objects

• Constant
• Holds a single value of a given type cannot
  change.
• Variable
• Holds a single value of a given type.
• New value of same type can be assigned
  (instantly)
• Signal
• Holds a LIST of values of a given type.
• Present value a set of possible future values
• New values can be assigned at some future time
  not now!
• Signals have ATTRIBUTES signalattribute
• File
• Contains a sequence of values of one or more
  types.
• Usually read or written to using procedures
• For simulation not synthesis

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Data Types

• Scalar Types
• Enumerated a list of values
• Integer
• Floating Point
• Physical with units, for physical quantities
• Composite Types
• Array (all of same type)
• Record (can be different types)
• Access Type
• File Type

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Enumerated Types

• CHARACTER one of the ASCII set
• BOOLEAN can be FALSE or TRUE
• BIT can be 0 or 1 (note single quotes)
• STD_LOGIC
• Has NINE legal values
• U, X, 0, 1, Z, W, L, H, -
• Example Declarations
• Type CAR_STATE is (back, stop, slow, medium,
  fast)
• Subtype GO_KART is CAR_STATE range stop to
  medium
• Type DIGIT is (0, 1, 2, 3, 4, 5, 6,
  7, 8, 9 )

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Integers

• All implementations support 32-bit integers, with
  a range of values from (231 1) to (231
  1)
• Integer data types with a smaller rage can be
  defined to save hardware (no sense forcing a
  32-bit counter when you need a 4-bit counter)
• Examples of legal integers
• 56349 6E2 0 98_71_28
• (Underscores can be thrown in anywhere, and dont
  change the value of the number.)

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Integers

• Type Declarations
• Type INDEX is range 0 to 15
• Type WORD_LENGTH is range 31 downto 0
• Subtype DATA_WORD is WORD_LENTH range 15 downto
  0
• Object Declarations
• Constant MUX_ADDRESS INDEX 5
• Signal DATA_BUS DATA_WORD

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Arrays

• An Array of type BIT is called a BIT_VECTOR
• signal MYSIG IN BIT_VECTOR( 0 to 3)
• An Array of type STD_LOGIC is called a
  STD_LOGIC_VECTOR
• signal yourSIG OUT BIT_VECTOR( 31 downto 0)
• A STRING is a character array
• csonstant GREETING STRING Hello!

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VHDL Key Idea

• A key idea in VHDL is to define the interface of
  a hardware module while hiding its internal
  details.
• A VHDL entity is simply a declaration of a
  modules inputs and outputs, i.e., its external
  interface signals or ports.
• A VHDL architecture is a detailed description of
  the modules internal structure or behavior.

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VHDL Interface - Ports

• You can think of the entity as a wrapper for
  the architecture
• hiding the details of whats inside
• providing ports to other modules

input port
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VHDL Conceptual Model

• VHDL actually allows you to define multiple
  architectures for a single entity
• it also provides a configuration management
  facility that allows you to specify which
  architecture to use during a particular
  synthesis run

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VHDL Program File

• In the text file of a VHDL program
• the entity, architecture, and configuration
  declarations are all separated
• not nested as the previous diagram may have
  implied
• We will use white space to set them apart

mydesign.vhd
entity
architecture
configuration
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Entity Declaration

• Specifies the name of the entity
• Lists the set of interface PORTS
• PORTS are SIGNALS that enter or leave the entity
• This is the black box, or block diagram view

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Entity Declaration
entity half_adder is port( A, B in BIT SUM,
CARRY out BIT) end half_adder entity
half_adder is port( A, B in BIT SUM
out BIT CARRY out BIT ) end entity
half_adder
White space is ignored
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Entity Declaration
entity half_adder is port( A, B in BIT SUM,
CARRY out std_logic) end half_adder entity
half_adder is port( A, B in std_logic
SUM out std_logic CARRY out std_logic
) end entity half_adder
Using IEEE 1164 standard signals and data types
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VHDL Signal Modes

• in means input-ONLY, you cannot use a mode in
  signal on the LEFT side of an equation (that is,
  you cant assign a new value to inputs)
• out means output-ONLY, you cannot use a mode
  out signal on the RIGHT side of an equation (that
  is, you cant use the outputs)
• inout means bi-directional, like a three-state
  bus, for example. This mode is typically used for
  three-state input/output pins on PLDs
• buffer means the signal is an output of the
  entity, and its value can also be read inside the
  entitys architecture

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Example LogicFcn
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Entity Declaration for LogicFcn
library IEEE use IEEE.std_logic_1164.all   entit
y LogicFcn is port ( A in std_logic B
in std_logic C in std_logic Y out
std_logic ) end entity LogicFcn  
A
B
Y
C
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Architecture Body

• Specifies the internal circuitry of an entity,
  using any one of the following modeling styles
• As a set of interconnected components, as wired
  (called structural modeling)
• As a set of concurrent signal assignment
  statements (called dataflow modeling)
• As a set of sequential assignment statements,
  i.e., a process (called behavioral modeling)
• As any combination of the above (called mixed
  modeling)

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Parts of Architecture Body
architecture ARCH_NAME of ENTITY_NAME is
ltdeclarative section list internal signals,
variables, and components here. For each
component used show the port map, (unless
port map defined is in a package)
gt begin ltstatement section all concurrent
statements and components and processes in
this section execute at the same time, NOT
sequentiallygt end ARCH_NAME
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Architecture Body (Dataflow)
With a signal assignment statement
  architecture dataflow of LogicFcn is begin Y
lt (not A and not B) or C end dataflow
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Architecture Body (Dataflow)
With a conditional signal assignment statement
  architecture dataflow of LogicFcn is begin Y
lt '1' when (A '0' AND B '0') OR
(C '1') else '0' end dataflow
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Architecture Body (Behavioral)
architecture behavioral of LogicFcn is begin
fcn process (A,B,C) begin wait on A,B,C
if (A '0' and B '0') then Y lt '1'
elsif C '1' then Y lt '1' else
Y lt '0' end if end process end
behavioral
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Architecture Body (Structural)
Internal signals are LOCAL to the Architecture,
and cannot be seen outside it !
A
B
Y
C
architecture
entity
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Architecture Body (Structural)
architecture structural of LogicFcn is signal
notA, notB, andSignal std_logic begin i1
inverter port map (i gt A,
o gt notA) i2 inverter port map (i gt B,
o gt notB) a1 and2 port
map (i1 gt notA, i2 gt
notB, y gt andSignal) o1
or2 port map (i1 gt andSignal,
i2 gt C, y gt Y) end
structural
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Components for Structural Model
component OR2 port ( i1 in std_logic
i2 in std_logic y out std_logic ) end
component component INVERTER port ( i in
std_logic o out std_logic ) end
component end primitive
library IEEE use IEEE.std_logic_1164.all package
primitive is component AND2 port ( i1 in
std_logic i2 in std_logic y out
std_logic ) end component 
these are component declarations