COMP3221: Microprocessors and Embedded Systems

1
COMP3221 Microprocessors and Embedded Systems

• Lecture 23 Memory Systems (II)
• http//www.cse.unsw.edu.au/cs3221
• Lecturer Hui Wu
• Session 2, 2005

2
Overview

• Memory Timing Requirements

3
Memory Timing Requirements
There are two components of timing requirements.

• Timing requirements from CPU.
• CPU generates control signals such as READ/WRITE,
  and in the absence of handshaking signals such as
  WAIT or READY, takes data from or put data on the
  bus at specific times.
• Timing requirements from memory.
• We will use SRAM as an example to illustrate the
  timing requirements from the point of view from
  the memory.

4
CPU Read and Write Cycles
The CPU control all reading and writing of
information.

• tCYC Cycle time The total time to complete a
  write or read cycle.
• tAD Address delay The delay from the start of
  the write or read cycle until the address appears
  on the external address bus. This delay accounts
  for multiplexing and other CPU-generated delay.
• tAV Address valid The time the address is
  valid on the external address. The CPU takes it
  away or changes it at the end of the read or
  write cycle.

5
CPU Read Cycle

• tRED Read enable delay The delay from the start
  of the read cycle until the read enable signal is
  asserted. This is found in CPUs that have
  separate READ and WRITE control signals.
• tRE Read enable pulse length The duration of
  the READ signal.
• tRDD Read data delay The CPU waits for this
  time before it reads the data from the data bus.
• tRDS Read data setup The time the data must be
  valid before they are read by the CPU.
• tRDH Read data hold The CPU may require the
  data to be held after it reads them.

6
CPU Read Cycle
tCYC
CPU Clock
ADDRESS
Address Valid
tAV
tAD
tRE
READ
tRED
Data Valid
DATA
tRDS
tRDH
tRDD
7
CPU Write Cycle

• tWDD Write data delay The CPU waits for this
  time before it places the data to be written to
  memory on the data bus.
• tWDV Write data valid The time the CPU keeps
  the data on the data bus.
• tWED WRITE enable delay The CPU waits for this
  time before it asserts the write enable signal.
• tWE Write enable pulse length The during of
  WRITE signal.
• tWDH Write data hold The time the CPU holds the
  data on the data bus after deasserting the write
  enable signal.

8
CPU Write Cycle
tCYC
CPU Clock
ADDRESS
Address Valid
tAV
tAD
tRE
WRITE
tWDH
tWED
tWE
Data Valid
DATA
tWDD
tWDV
9
Memory Read Cycle

• tRC Read cycle This the total time for the read
  cycle.
• tACS Chip select access The maximum time
  required by the memory for the CS to be asserted
  before the data are available.
• tAA Address access This is the maximum time
  required by the memory for the address to be
  present before the data are available.
• tRDHA Read data hold after address The time the
  memory may hold the data at the output after the
  address is changed.
• tRDHC Read data hold after chip select The
  minimum time the chip will hold the data after
  being deselected.

10
Memory Read Cycle (Cont.)

• tOE Output enable access On chips that have an
  output enable, this parameter gives the maximum
  time for the chip to respond with the data.
• tOHZ Output enable to out high Z On chips that
  have an output enable, this parameter specifies
  the time the data will remain valid before going
  into three-state (high impedance).

There are two times for reading data are
important to memory designers. The read cycle
time, tRC, is the minimum time that the address
must be stable (unchanging) at the chip. The
address access time, tAA, is the maximum time
required by the memory before the data are
available.
11
Memory Read Cycle (Cont.)
tRC
ADDRESS
Address Valid
CS
tRDHA
tACS
tRDHC
tAA
DATA
Data Valid
tOHZ
tOE
OUTPUT ENABLE
12
Memory Write Cycle

• tWC Write cycle This is the minimum total time
  required by the memory to complete a write cycle.
  This may or may not the same as tRC.
• tCW Chip selection to end of write The minimum
  time the CS signal must be asserted.
• tAS Address setup The minimum time the address
  must be valid before the WRITE signal is
  asserted.
• tMWE Write enable The minimum time the WRITE
  signal must be asserted.
• tAW Address valid to end of write The minimum
  time the address must be valid.

13
Memory Write Cycle (Cont.)

• tWDS Write data setup The minimum time the data
  must be valid before the end of write enable.
• tMWDHE Write data hold after enable The minimum
  time the data must be valid before the WRITE
  signal is deasserted.

14
Memory Write Cycle (Cont.)
tWC
ADDRESS
Address Valid
tCW
CS
tAS
tMWE
WRITE
tWDHE
tAW
tWDS
DATA
Data Valid
15
Reading

• Chapter 9 Computer Memories. Microcontrollers
  and Microcomputers by Fredrick M. Cady