CS 221 IT 221 Lecture 05

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CS 221/ IT 221Lecture 05

• Processors
• Machine code and
• instruction execution
• Dr. Jim Holten

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Von Neumann Architecture
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Processor Structure

• Control Unit
• Arithmetic Logic Unit
• Memory Bus
• I/O Bus

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Control Unit Structure

• System Clock
• Instruction Handling Registers and Logic
• Memory Bus Control Logic
• I/O Bus Control Logic
• Arithmetic Logic Unit Control Logic

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Arithmetic Logic Unit Structure

• General Registers
• Index Registers
• Arithmetic Operations Logic
• Boolean Operations Logic

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Control Unit Behavior

• Finite State Machine (FSM) that sequences through
  the stages of each instructions execution
• Actual state transition sequence controlled by
  the op codes and the system clock
• Each state transition initiates or controls a
  combination of concurrent activities

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System Clock

• Controls the timing on the FSM transitions
• Prevents activities from running too fast for the
  internal logic delays
• Prevents race conditions in operations
• Synchronizes all the system activities

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Instruction Handling Logic

• Instruction fetch control
• Instruction decoder
• Execution control for each operation
• Data
• fetch from memory
• store to memory
• I/O
• Input from device
• Output to device

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VNA with Buses
CS 221/ IT 221
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Memory Bus Structure
CS 221/ IT 221
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Bus Structures

• Data portion Where the data bits are passed
  back and forth (or instructions being fetched)
• Address portion The address of the device or
  memory location for the data source or
  destination
• Control flags Advises memory controller and
  device controllers
• When an address is valid
• Whether data is being fetched or stored
• When the data is valid

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Data Store Cycle

• Indicate the address and data are NOT valid
• Store the address onto the address bus
• Indicate this is a STORE action
• Store the data onto the data bus
• Indicate the address is valid
• Indicate the data is valid

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Data Fetch Cycle

• Indicate the address is NOT valid
• Place the address on the address bus
• Indicate it is a FETCH operation
• Indicate the address is valid
• When the memory or device indicates the data is
  valid store it into the internal register(s).
• Indicate the address is no longer valid

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Instruction Execution Cycle

• Fetch instruction (data from a memory address)
• Decode instruction
• Op code
• Flags
• Registers to use
• Addresses to access
• Perform instruction
• Fetch any memory operands
• Perform the operation (usually stores results
  into registers)
• Store any memory results

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Instruction Type Categories

• Data Movement
• Arithmetic Operations
• Boolean Logic Operations
• Bit Manipulation Instructions
• I/O Instructions
• Transfer of control (jump, call, return)
• Special Purpose Instructions (Interrupt control,
  etc)

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Instruction Set Properties

• Coverage can the set do everything?
• Orthogonality the avoidance of redundancy
• Performance tradeoffs
• Less memory access by using more registers, etc.
• RISC instruction sets for faster execution

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Instruction Set Types

• Basic
• Micro code
• Expanded instruction set
• Reduced instruction set (RISC)?

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Addressing Modes

• No Addressing
• Immediate Addressing (data in the instruction)
• Direct Addressing
• Registers
• Memory Locations
• Indirect Addressing
• Register content is a pointer
• Memory location is a pointer

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Addressing Modes (cont)

• Indexed addressing
• Index register added to the address
• Base register added to the address
• Stack base address is used
• Many other variations

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Instruction Execution Variations

• Instruction execution pipelines (one pipeline,
  purge and start over on jumps, calls, and
  returns)
• Instruction execution vectoring (multiple
  lookahead pipelines for each possible execution
  path, purge those that dont apply after each
  instruction)
• Pipeline control instructions (bit patterns in
  the instruction control activities at each stage
  of the pipeline)
• Associative processing may be concurrent and
  asynchronous.