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Computer Systems

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Three operands except for load/store. Load: load data from memory to register ... STORE r1,I ; I = r1. M68000 (If both I and J are memory locations) MOVE J,D0 ; D0 = J ... – PowerPoint PPT presentation

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Title: Computer Systems


1
Computer Systems
  • Overview of
  • Instruction Set Architecture

2
Overview of ISA
  • Instruction
  • Operand
  • Operation repertoire
  • Data types
  • Addressing modes
  • Registers
  • Procedure call mechanism

3
Instruction
  • An instruction is an op-code followed by
    address(es)
  • Address means any address in system
  • Registers, memory locations, I/O ports, etc.
  • Format
  • Layout of bits in an instruction
  • Usually more than one instruction format in an
    instruction set
  • Length of instruction
  • Length of op-code field(s)
  • Style
  • Number of addresses

4
Instruction Style
  • Four-address format
  • Op-code Src1 Src2 Dst NextInstr
  • z ? x op y
  • Src1 x, Src2 y, Dst z
  • Three-address format
  • Op-code Src1 Src2 Dst
  • Use program counter for next instruction
  • Two-address format
  • Op-code Src1 Src2 (and Dst)
  • y ? y op x
  • Src1 x, Src2 and Dst y
  • Example M68000

5
Instruction Style
  • One-address format
  • Op-code Src1
  • AC ? AC op x
  • Src1 x, Accumulator (AC) is Src2 and DST
  • Zero-address format
  • Op-code
  • Use stack
  • push(pop(stack) op pop(stack))
  • Post-order expression

6
Instruction Style
  • Load-store style (3-address format)
  • All operations occur in registers
  • Three operands except for load/store
  • Load load data from memory to register
  • Store store data from register to memory
  • Op-code r1 r2 r3
  • r3 ? r1 op r2
  • r1, r2, and r3 are registers
  • Example MIPS

7
Example I J K
  • Four-address format
  • ADD J, K, I, NEXT I J K
  • next instruction in location NEXT
  • Three-address format
  • ADD J, K, I I J K
  • next instruction in PC
  • Two-address format
  • MOVE J, I I J
  • ADD K, I I K I

How about ADD K, J MOVE J, I
8
Example I J K
  • Load-store style
  • LOAD J,r2 J r2
  • LOAD K,r3 K r3
  • ADD r1,r2,r3 r1 r2 r3
  • STORE r1,I I r1
  • M68000 (If both I and J are memory locations)
  • MOVE J,D0 D0 J
  • ADD K,D0 D0 K
  • MOVE D0,I I D0

9
More Examples
  • I J K L
  • I J K L
  • I (J K) L
  • I (J K) L M
  • I J K L M
  • I J K (L M)
  • I (J K) (L M)

10
Conclusion on Instruction Style
  • Which one is better?
  • Compare
  • Instruction counts
  • Instruction length
  • Memory accesses

11
Operands
  • Addresses
  • Memory locations, registers
  • Numbers
  • Integers, floating point numbers
  • Characters
  • ASCII etc.
  • Logical Data
  • Bits or flags

12
Operation Repertoire
  • Types of Operation
  • Data Transfer
  • Arithmetic
  • Logical
  • Conversion
  • I/O
  • System Control
  • Transfer of Control
  • How complex are they?
  • RISC (Reduced Instruction Set Computer) vs.
  • CISC (Complex Instruction Set Computer)

13
Addressing Modes
  • Where to find the data items, i.e., operands
  • Common addressing modes
  • Immediate
  • Direct
  • Indirect
  • Register
  • Register Indirect
  • Displacement (Indexed)
  • Post-increment and pre-decrement
  • Etc.

14
Registers
  • The sketch pads in CPU
  • Design isuues
  • Number and size
  • General purpose
  • Specialized
  • User visible
  • Control and status

15
Last but not the least - Endian
  • Byte order problem
  • What order do we read numbers that occupy more
    than one byte
  • e.g. (numbers in hex to make it easy to read)
  • 12345678 can be stored in 4x8bit locations as
    follows
  • Address Value (1) Value(2)
  • 184 12 78
  • 185 34 56
  • 186 56 34
  • 187 78 12
  • read top down or bottom up?

16
Endian
  • The problem is called Endian
  • The system on the left has the most significant
    byte in the lowest address
  • ? This is called big-endian
  • The system on the right has the least
    significant byte in the lowest address
  • ? This is called little-endian
  • Big-endian examples M68000, Internet
  • Little-endian example Intel x86
  • Why is it a problem?

17
Example Register Organizations
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