Interface and Defect States at Ultrathin SiO2HfO2SiO2Si Junctions

1
Interface and Defect States at Ultrathin
SiO2/HfO2/SiO2/Si Junctions
M. Bataiev, S.P.Tumakha, Y. M. Strzhemechny, S.H.
Goss, and L. J. Brillson The Ohio State
University, Columbus, OH
C.L. Hinkle, C.C. Fulton, and G. Lucovsky North
Carolina State University, Raleigh, NC
Abstract We used low energy electron-excited
nanoscale (LEEN) depth-resolved luminescence
spectroscopy and secondary ion mass spectrometry
(SIMS) to measure native defect and chemical
distributions within ultrathin SiO2/HfO2/SiO2/Si
gate dielectric stacks and their changes with
high temperature annealing. These distributions
vary significantly between upper and lower HfO2
interfaces. Pronounced decreases (increases) in
SiO2 (HfO2) defect emissions are consistent with
increased HfO2 crystallinity and decreased oxide
trapped charge / interface state densities in
corresponding transistor structures.

• 900 C Anneal
• - increases 3.5 /2.7 eV intensity ratio by 5 x
  at outer SiO2/HfO2 interface 2-3x deeper into
  stack
• - increases 4.2 /2.7 eV intensity ratio by gt20 x
  at outer SiO2/HfO2 interface gt10 x deeper into
  stack
• - 4.2/3.5 eV intensity highest inside HfO2 layer

I. Motivation Multiple Challenges as Chip
Densities Increase Mesoscopic Scaling Requires
Ultrathin Oxides, Higher-K Dielectrics, and/or
New Architectures
Promising Approach First create ultrathin, ideal
SiO2/Si template layer (low interface state
density), then high-K dielectric layer, then cap
Higher-k Dielectrics Thicker dielectric with
same capacitance C ?A/ d gt 4 x 10-6 F-cm2 and
limited tunneling I exp -4?d(2?Ecmeff)1/2
for d lt 1.5 nm ?(HfO2)30 vs ?(SiO2)3.9 ? HfO2
d can be 30/3.97.7 times larger at constant C
Low Interface State Oxide Trapped Charge
Densities Dit , Not lt 1010 cm-2-eV SiO2
Dielectric of Choice for Metal-Oxide-Semiconductor
(MOS) High-K dielectrics Dit 1012-1013 cm-2
Low Thermal Budget Processing Minimize
Reaction, Interdiffusion During Fab ? Optimize
bonding, composition, architecture ? Rapid
Process Optimization
Challenges Assess local defect changes vs.
processing spectroscopically (LEEN)
900 ?C Anneal
III. Results
Analogous As-Grown High C-V trapped charge
density

• Annealed Outer HfO2/SiO2 Interface 2 x Sharper
  Inner Interface H Removed

Analogous 800 C Annealed gt10 x lower trapped
charge density
Vfb 0.24 eV ? Qf - 6x1012 cm-2
at SiO2-Al2O3 interface
Vfb 0.008 eV (same as Si-SiO2) ? Qf lt 1011
cm-2 at self-organized, matched SiO2-HfO2-Al2O3
interface
(Si doping 2-3x1018 cm-3)
900 ?C Anneal

• H in HfO2 Decreases by 3 x with Annealing
• C Increases by 3 x Near Both Interfaces with
  Annealing

IV. Analysis
in-plane self-organization similar to Si-SiO2 -
both reduce SiO2 defect luminescence
c-HfO2
High C and low tunnel I requires optimizing K,
?EC, and meff
G. Lucovsky et al., J. Vac. Sci. Technol. B22,
2132 (2004)
SiO2 defects
HfO2s high K advantage only partially offset by
lower ?Ec and meff
II. Experimental Technique UHV glancing incidence
or SEM electron beam excites electron-hole pairs
and recombination involving defect states.
Energy-dependent depth of excitation enables
probe of localized states, heterojunction band
gaps, new compounds, and ultra-thin layers on a
nm scale.

• 1.9 and 2.7 eV emissions correspond to SiO2
  defects (NBOHC and E)
• New emission at 3.5 and 4.2 eV ? HfO2 film and
  interfaces
• 900 0C RTA anneal increases (decreases) HfO2
  (SiO2) features

NBOHC
After 900C anneal - i) increase in HfO2 grain
size in HfO2 layer ii) chemical phase
separation into SiO2 and HfO2 to reduce in-plane
strain at Hf silicate interface and iii)
compaction of SiO2
Depth Dependence of Defect Emission Effect of
Annealing
Courtesy P.M. Lenahan, Penn State

• V. Conclusions
• LEEN provides nm-depth-resolved measurements of
  defects in multi-layer dielectric stacks
• As-deposited stacks dominated by SiO2 E and
  NBOHC defects
• Annealed stacks dominated by HfO2 defects,
  localized to outer SiO2-HfO2 interface
• Annealing reduces SiO2 defects, increases HfO2
  crystallization
• Defect and electrical changes correlate
  ?Potential for in-situ optimization

Acknowledgements This work is supported
by the Office of Naval Research (Colin Wood), the
Department of Energy (Jane Zhu), and the
Semiconductor Research Corporation.

• SiO2 and HfO2 defects exhibit different depth
  dependences /origins
• Annealing increases 2.75 eV peak at outer SiO2
  /HfO2 interface
• 3.5 eV dominant with annealing Max near outer
  SiO2 /HfO2 interface
• Annealing either increases 3.5 eV emission or
  decreases SiO2 features

JEOL JAMP-7800F SEM