Timing Verification of VLSI Circuits

1
Timing Verification of VLSI Circuits

• Professor Weiping Shi
• http//ece.tamu.edu/wshi/689.html

2
I. Introduction

• What is EDA?
• Technology trend
• Design flow
• Timing verification flow

3
Technology Trend

• International Technology Roadmap for
  Semiconductors (ITRS)
• World-wide and industry-wide cooperation since
  1992
• Consensus on RD needs out to a 15 year horizon

4
ITRS Trend for Scaling
5
Implication

• Signal propagation becomes more difficult due to
  increasing capacitive and inductive coupling
• Signal integrity degrades and cause both timing
  uncertainty and potential logic errors

6
Implication

• Testing
• Decreasing pin/gate ratio
• Delay fault v.s. stack-at fault
• Low power
• Heat already a big problem
• Wireless applications
• More

7
MPU/ASIC Design Flow
Design Spec
Behavioral Design
Verify Function
Logic Synthesis
Verify Function
Physical Synthesis
Verify Timing and Function
8
Timing Verification

• Synthesized circuits meet timing constraints
• Post-synthesis verification
• Use simple estimation such as unit delay
• Post-layout verification
• Use accurate interconnect and gate parasitic
• Design closure

9
Design Closure
Bad Timing Verification
Number of Paths Violating Timing Constraints
Good Timing Verification
Iterations
10
What to Verify?

• Synchronous circuit and scan design
• Combinational circuit between flip-flops
• Setup time, hold time, clock skew, etc

Combinational Circuit


clock
11
Setup Time Violation

• Setup time constraint of a flip-flop specifies a
  time interval before the active edge of clock
• Data must arrive before the interval

Clock
Data
Data
OK
Clock
Data
Violation
12
Hold Time Violation

• Hold time constraint of a flip-flop specifies an
  interval after the active edge of clock
• Data must be stable in the interval

Clock
Data
Data
Violation
Clock
Data
OK
13
Clock Skew

• Signal skew is the arriving time difference
  between two signals
• Clock skew between any two leaves must be within
  the requirement

14
Timing Verification Flow
Layout (gds2, LEF/DEF)
Cell Library
Netlist
Interconnect Parasitic Extraction
Model Order Reduction
Delay Evaluation
Paths Violate Timing Constrains
Timing Analysis
15
Example
a
y
b
XOR
NAND
NAND
b
a
y
Layout Synthesis
16
Step 1. Parasitic Extraction
s1
XOR
NAND
NAND
s2
a
Distributed RC R1 R2 R3 parasitic res C1 C2 C3
parasitic cap Cxor Cnand gate sink cap
R1
Cnand
Cxor
R2
R3
a
s1
s2
Parasitic Extraction or each net
C3
C1
C2
17
Step 2. Model Order Reduction
s1
s2
R1
Cnand
Cxor
R2
R3
a
s1
s2
transfer functions
C3
C1
C2
h1
s1
h2
s2
a
? load
Model Order Reduction
18
Step 3. Delay Evaluation
50 buffer-to-buffer delay at s1
Buffer-to-buffer Delay Time for signal to
travel from input pin of a gate to input pin of
next gate
h1
s1
h2
s2
a
50 buffer-to-buffer delay at s2
19
Step 4. Timing Verification

• Dynamic
• Input vector based
• Expensive when circuit is large
• Static
• Independent of input vectors
• Critical path search
• Fast, but may overestimate

20
Signal Coupling
Coupling Capacitance
Noise
21
Crosstalk

• Cross talk affects delay

0?1
nominal delay
0
0?1
delay increased
1?0
0?1
delay reduced
0?1
22
Verification and Testing

• Timing verification identifies paths that violate
  timing constraints
• Timing verification also identifies paths are
  likely violations
• A near violation can be a true violation under
  combination of defects, process variations and
  signal coupling
• Delay fault testing

23
Conclusion

• Technology trend decides important and urgent
  areas of research
• Timing verification is a central part of design
  cycle, and directly affects design cycle and time
  to market
• Timing verification for next generation VLSI
  circuits is increasingly important

24
Assignments 1

• Read ITRS (http//public.itrs.net/) and for the
  area of your interest, identify issues that are
  important
• Go to MOSIS (http//www.mosis.com) and check
  their technology file, SPICE models and design
  rules