VECTOR IRAM

1
VECTOR IRAM A Media-Oriented Vector Processor
with Embedded DRAM
http//iram.cs.berkeley.edu/
Joe Gebis, Christos Kozyrakis, Sam Williams, Dave
Patterson

• Vector Instruction Set
• Complete load-store vector instruction set
• Uses the MIPS64 ISA coprocessor 2 opcodes
• Data types supported 64b, 32b, 16b
• 32 general-purpose vector registers, 16 vector
  flag registers, 16 scalar registers
• 91 instructions arithmetic, logical, vector
  processing, sequential-strided-indexed loads and
  stores
• Not fixed in the ISA
• Maximum vector length
• Width of datapaths in functional units
• DSP support
• Fixed-point multiply-add, saturated arithmetic
• Simple intra-register permutations for reductions
  and FFT
• Compiler and OS support
• Conditional execution of vector instructions
• MMU-based virtual memory

• Architecture
• Single-issue 5Kc MIPS core with 8KB caches
• Vector unit
• 8 KByte vector register file
• 2 arithmetic (1 FP), 2 flag, 1 memory unit
• 256b datapaths per functional unit

Motivation Applications

• Embedded multimedia systems
• Small size, battery-operated, portable or
  embedded devices

• Multimedia input and output (speech, video)
• Integrated functionality (PDA, cell-phone, camera
  etc)

• Processor features for embedded multimedia
• High performance on demand for multimedia without
  continuous high power consumption
• Tolerance to memory latency
• Scalable in performance and complexity
• System-on-a-chip integration
• Mature, HLL-based software model

• Memory System
• Eight 13-Mb DRAM macros
• Crossbar interconnect (2x 12.8 GB/s peak)
• Up to 5 independent addresses issued per cycle
• Can sustain up to 64 pending accesses

• Chip Statistics
• Technology IBM SA-27E
• 0.18mm CMOS, 6 metal layers (copper)
• 325 mm2 die area (18.9mm x 17.6mm)
• 158 mm2 for DRAM, 70 mm2 for logic
• Transistor count 125M
• 1.2V logic, 1.8V DRAM

• Test System
• Based on the MIPS Malta development board
• PCI (x4), Ethernet, AMR (audio), IDE (x2), USB,
  CompactFlash, PS/2 (x2), parallel, serial (x4),
• VIRAM daughter-card
• Modified MIPS daughter-card for the 5Kc core
• VIRAM processor
• Galileo GT64120 system controller
• 32-Mbyte external DRAM (1 DIMM)

Vector Lane

• Implementation Design
• Design styles
• Vendor Verilog IP MIPS core, FPU
• Local Verilog vector control, vector lanes
• Full custom vector register file, crossbar
• Macros DRAM, scalar caches
• Verification
• Full functional simulator (written in C) to
  verify against
• Set of 2500 directed tests and additional random
  tests used to verify design
• Tests automatically distributed to cluster of
  testing machine

• Modular vector unit design
• Single 64b lane block replicated 4 times
• All lanes receive identical control signals
• Minimal cross-lane communication
• Basic replication block for scaling
• Reduced design and test time

• Power consumption
• 2W at 1.2V
• Package
• 304-lead quad ceramic package
• Peak performance
• 1.6/3.2 /6.4 Gops (64/32/16b ops)
• 2.4/4.8/9.6 Gops (with multiply-add)
• 1.6 Gflops (single-precision)