PreFPIX2Tb DAC Response

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Radiation Tolerance
D. C. Christian, J. A. Appel, G. Chiodini,
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B. Hall, J. Hoff, S. Kwan, A. Mekkaoui,
Tests of a Prototype
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R. Yarema, W. Wester, S. Zimmermann,
Pixel Readout Chip
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For BTeV
Fermilab
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1TeV p
1TeV p
Luminosity2x1032 cm-2s-1 (lt2gt interactions each
132 ns)
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FPIX Roadmap

• Pixel size 50m x 400m (matches ATLAS n on n
  test sensors)
• Target rad-hard technology Honeywell 0.5m CMOS
  (SOI)
• (3 metal, 3.3V) (1 metal layer used for shield
  between sensor R/O chip)
• FPIX0 (1997) HP 0.8m CMOS
• Close to final analog front end
• R/O pixel includes a peak sensor digitized off
  chip
• Array size 12 x 64
• Bench tests and beam tests
• FPIX1 (1998) HP 0.5m CMOS
• Optimized front end
• 4 comparators per cell (2-bit FADC)
• New fast R/O architecture, allows both
  self-triggered and externally-triggered operation
• Array size 18 x 160
• Bench tests and beam tests
• Then (Dec, 1998), a change of plans

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FPIX2 Roadmap

• 0.25m CMOS
• (5 metal 6 possible, 2.5V)
• Design for 2 vendors (lowest common
  denominator design rules)
• CERN Very favorable contract, but problems
  with US Gov. restrictions
• Taiwan Semiconductor Manufacturing Corp (TSMC)
  Available through MOSIS
• PreFPIX2T (1999) TSMC 0.25m CMOS
• New analog front end, with new leakage current
  compensation strategy
• 8 comparators per cell (3-bit FADC) no EOC logic
  included
• Array size 2 x 160
• Bench tests (g radiation exposure)
• PreFPIX2I (2000) CERN 0.25m CMOS
• Same front end
• Complete core including new, simplified EOC
  R/O (self-triggered only)
• Array size 18 x 32
• Bench tests (proton exposure)

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Total Dose Tolerance

• Threshold shifts g and hadrons.
• Small as expected.
• Surface leakage currents g and hadrons.
• Negligible by design (gate all around NFETs and
  guard rings).
• Bulk damage hadrons.
• Small, manageable, increase in leakage due to
  parasitic device formation.

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Single Event Effect Tolerance

• Catastrophic events gate rupture, latch up.
• None observed ? rate guaranteed to be acceptable
  to BTeV.
• Soft errors single event upset.
• Small cross sections measured
• (1 6 x 10-16/cm2) ? no need for redundant
  logic or other design measures.

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Radiation damage to CMOS transistors
Positive charge trapped in the oxide layer
effectively biases the transistors.
Gate oxide
Gate
n
n
Source (normally connected to gnd)
Drain
p bulk
Conductive channel is induced by positive voltage
applied to the gate
Threshold voltage shifts with exposure to
radiation BUT, the effect gets smaller as the
oxide gets thinner (with smaller feature size)
by 0.25m the threshold shifts are small enough to
be benign.
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Radiation induced leakage current
Trapped charge in the field oxide also causes
leakage current in nmos devices by inducing an
n-channel in the p-bulk.
source
drain
pmos leakage current does not increase (glass
charges doesnt induce a p-channel).
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Rad-hard nfet layout (very schematic!)
gate all around layout (guard rings to prevent
current between devices (can cause latchup) not
shown)
Large W/L is easy
Small W/L is hard
Or, impossible!
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(No Transcript)
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Irradiation Tests

• g Irradiation (60Co at Argonne National Lab)
  individual transistors and FE prototype 58 MRad,
  preFPIX2T 33 MRad.
• 200 MeV proton irradiation (Indiana University
  Cyclotron Facility) preFPIX2I 26 MRad
  (4.4x1014/cm2), preFPIX2Tb 43 MRad
  (7.4x1014/cm2).

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Front end response, before and after 33 MRad 60Co
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Front end response, before and after 26 MRad 200
MeV p
DC shift believed to result from increased
leakage to bulk.
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preFPIX2I noise, before and after 26 MRad proton
irradiation
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PreFPIX2Tb DAC Response
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Total Dose Effect on FPIX

• Small increase in gain decrease in dynamic
  range.
• Small increase in DAC nonlinearity.
• Small decrease in front end noise.
• Small decrease in discriminator threshold
  dispersion.
• ? Design verified to be sufficiently radiation
  tolerant.

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200 MeV proton irradiation tests
Devices Under Test
LVDS driver board
200 MeV Protons
PCI-PTA Card
LVDS driver board
GPIB
100 foot twist-n-flat to PTA card
2.5V Power Supplies
Laptop
Concrete walls

• SEU Test Procedure download pattern, wait 1
  minute, read back check for errors, repeat.
• Irradiation done in air at room temperature.
• No low energy particle or neutron filter.
• Nominal flux 2 x 1010 protons/(cm2s).
• 1.5 cm beam spot diameter measured with a
  sensitive film (flux 90 center value).
• Laser spot alignment and remote video
  monitoring.
• Dosimetry Faraday cup SEM.

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FF in DAC (112 in chip)
Single Event Upset Expectations
Due to the symmetric configuration 0 ? 1 and 1 ?
0 are expected to be equally likely.
FF in SR (1152 in chip)
Due to asymmetric configuration 1 ? 0 SEU is
expected to be two times more likely than 0 ? 1.
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Single Event Upset Cross Sections
transition from 0 to 1. transition from 1
to 0.
April 01 Aug 01
April 01
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Estimated SEU Rate in BTeV