Single Inclusive Jet Cross Sections at D0

1

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D? Collaboration Meeting, October 11 - 13, 2000,
Fermilab
Status of the L1 Trigger
Levan Babukhadia
SUNY at Stony Brook
http//www-d0.fnal.gov/blevan
2
CTPT/FPS Components

• Analog (Fermilab - DØ)
• AFE-8MCM (primarily CFTax)
• 10 here, ready by 11/01, 54 more by 12/15,
  balance 01/30/01
• Crates/Cables on hand, installed when required
• Power supplies delayed until new year (partial).
• Mixer ( Fermilab - CD )
• Super-sector (1/5th) mid-November
• Full Mixer 1/01
• Digital ( Fermilab - DØ )
• All MBs here and in testing
• Transition boards expecting in 2 weeks
• CTPT DBs (single-wide, 5 Virtex 2.5v FPGAs) by
  mid-November
• FPS DBs (double-wide, 3 Virtex 2.5v FPGAs)
  partial order out
• Xilinx/Virtex FPGAs for CTOT on order, others
  held until further decision, Virtex vs. Virtex-E
• Crates/Cables/PS all here by mid-November

3
CTTP/FPS Firmware CFT/CPS Axial

• DFEA (80) Jamieson Olsen (Kin is gone)
• Both L1/L2 firmware in good shape
• 4 FPGAs find tracks in 4 Pt and report to 5-th
  FPGA and to Muon
• Backend (5-th) FPGA does CPS cluster finding and
  track matching
• firmware has to be re-written, concerns on the
  chip size
• expect functional and tested firmware in a couple
  of months
• CTOC (8) Juan Lizarazo, now Ricardo Rodrigez
• Both L1/L2 firmware completed and tested in
  testbench
• Minor issues and additions will be addressed by
  Ricardo/Manuel
• CTQD (4) Pavel Polozov now gone
• L2CFT part completed functionally with some minor
  issue
• Needs implementation, L2CPS, and all of this
  tested in the hardware
• CTTT (1) Jerry Blazey
• Algorithm/VHDL/Functional/Implementation at 20
• 2 out of 64 Trigger Terms done through the
  implementation phase
• L1-gtL3 sender, finish all VHDL, implementation,
  hardware test stand

4
CTTP/FPS Firmware CPS Stereo

• DFES (5) Qichun Xu, MSU
• No link to L1 TM, straight to L2 and L3, thus has
  time!
• Main issue is cluster finding in the large number
  (500) of CPS stereo strips in a sector but
  having time may save the day...
• New MSU student Qichun Xu, just started
• Made a good head-start with an overall algorithms
  and the cluster finding algorithms in particular
  
• Start writing VHDL, expect functional code in
  about 1-2 months
• CPSS (2) ?!
• Nobody yet! Perhaps Qichun will take on this one
  as well ...

5
CTTP/FPS Firmware FPS

• DFEF (32) Levan Babukhadia
• Challenge cluster finding in 144 FPS strips at
  the L1 rate
• L1 U/V algo developed, coded, and implemented
  test stand is next
• L1U and L1V each takes Xilinx/Virtex 400 FPGA
  (75, 63 MHz)
• Develop L2 priority reporting algo to take care
  of truncation. It is aimed at the 3rd FPGA
• Transferring clusters within a DB or find
  clusters anew?...
• FPSS (4) Mrinmoy Bhattacharjee
• L1 algo developed, coded, and implemented w/o the
  L3 sender
• fits in one Xilinx/Virtex 400 FPGA (30, 66 MHz)
• Develop L2 algorithm
• FPTT (1) Satish Desai
• L1 algo developed, coded, and implemented w/o the
  L3 sender
• fits in one Xilinx/Virtex 400 FPGA (20, 64 MHz)
• Complete all L1 functionally, test stand by the
  end of October

6
CTPT/FPS Installation/Commissioning

• Assembling test stands for digital/VHDL testing
• Hardware 2 PCs, MBs, 2 Data Pump Boards, PS,
  cables, CTPT/FPS DBs
• 1 fully stuffed double-wide DB
• 10 fully stuffed single-wide DBs
• Personnel Jamieson Olsen, Brian Connolly (very
  short time), Ricardo Rodrigez, and a new
  part-time tech
• Had 1 working test stand but recently moved to
  DAB3/NE will be made operational this week
• Aiming at having 2 single board bench-tops and
  1 multi-board test stand (for a one sparse
  system test -- available now, Jamieson)
• Installing cables/crates on platform
• Crates/Cables installed in MCH

7
Luminosity Monitor Status

• Components
• Scintillator (48) complete
• CAFÉ boards (175) on hand
• Completing ADC (12) board layout, ordering parts
• Vertex board, FPGA 75 complete, layout
  commencing
• Procuring signal cables (60) soon
• Crate/PS on hand
• Installation/Commissioning
• Installed scintillator (4/00)
• Cabling awaits FPS, commissioning thereafter
• Software/Firmware
• Working on embedded software
• Download currently underway
• Database under development
• Schedule (on time)
• Electronics installed, February 1 Lum Monitoring
  March 1
• And/Or terms, March-April

8
L1 Calorimeter Trigger Status

• Timing signal generation and distribution
• Some work has been done and some tests have been
  made
• Initial implementation will probably cover just
  the CC racks
• L2/L3 readout complete (by November)
• Uses much of the same equipment as the readout
  from the TF
• All circuit boards exist and initial designs of
  all the FPGAs exist
• Analog input circuit (pick-off) boards (320)
• Prototypes of this exist and some testing has
  been done
• 1FTE month to production
• Quadrant Terms
• Circuit board (40) and FPGA design work has been
  started
• No prototypes exist yet
• Will not be pushed in the immediate future
• Schedule (late but well before 3/01)
• Inactive until TF complete 11/00. Resume within a
  month
• Start with analog pick-offs

9
L1 Muon Trigger Status

• L1MU Hardware (4 crates, prod beginning UAz)
• Crate Manager (MTCM)
• Production card testing in progress
• Motherboard (MTCxx - Trigger Card)
• Production cards beginning fabrication
• Flavor Boards
• Production Trigger Manager (MTM) boards ready for
  fabrication
• Production wire DB (MTC10) design in progress
  (finish in 2 weeks)
• Preproduction scintillator DB (MTC05) in
  fabrication
• SLDBs (Gbit/s Serial Links)
• Production board testing in progress
• Software/Firmware
• Download infrastructure in place
• Preproduction versions of all firmware exist
• No alarms, monitoring

10
L1 Muon Trigger Status

• MCEN Hardware (5 crates, in preprod testing BU)
• Crate Manager (MCCM)
• Preproduction card layout in progress
• Centroid Finder Cards (MCEN)
• Preproduction card testing in progress
• Physics Boards (MCPB)
• Preproduction board testing in progress
• Infrastructure
• Custom VME backplanes completed
• Power supplies
• Prototype assembled and tested
• VICOR supplies ordered but with 20-22 week lead
  time
• Platform Services -- on hold pending final cable
  plant design
• Cabling (1,600)
• Production at Fermilab and NIU in progress

11
L1 Muon Trigger Status

• Near Term Commissioning Goals
• Mid-August
• Stable operation of one (sparse) L1MU trigger
  crate and the L1MU MTM crate
• still using preproduction cards
• Early October
• Add L1CTPT MTM crate to the above
• Mid-October
• Begin commissioning production of L1MU crates and
  cards
• Longer Term Commissioning Goals
• Begin full crate testing in late Dec or early Jan
• Two octant triggering until then
• MCEN cards 2 months behind above
• Temporary power supplies for full crate tests

12
Trigger Framework Status

• All equipment operational and installed
• Defective SCL cables are being repaired
• L3 readout
• Finish up making readout to L3 available for
  normal use (by 1/11)
• Master Clock synchronization with the Tevatron
  beam
• This work now starting
• Operational permit
• Need to install 5 fuse blocks and write the
  documentation
• L1 Specific Trigger Fired Mask to L2
• Needed to make the Pseudo-Terms work
• Deferred until some progress on getting L1 Cal
  Trigger running again
• Firmware
• Completion of pseudo-terms
• Commissioning run-control
• Personnel
• Major loss of two engineers. Replacement uncertain