2Hardware Design Basics of Embedded Processors

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2-Hardware Design Basics of Embedded Processors
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Outline

• Introduction
• Combinational logic
• Sequential logic
• Custom single-purpose processor design
• RT-level custom single-purpose processor design

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Introduction

• Processor
• Digital circuit that performs a computation tasks
• Controller and datapath
• General-purpose variety of computation tasks
• Single-purpose one particular computation task
• Custom single-purpose non-standard task
• A custom single-purpose processor may be
• Fast, small, low power
• But, high NRE, longer time-to-market, less
  flexible

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CMOS transistor on silicon

• Transistor
• The basic electrical component in digital systems
• Acts as an on/off switch
• Voltage at gate controls whether current flows
  from source to drain
• Dont confuse this gate with a logic gate

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CMOS transistor implementations

• Complementary Metal Oxide Semiconductor
• We refer to logic levels
• Typically 0 is 0V, 1 is 5V
• Two basic CMOS types
• nMOS conducts if gate1
• pMOS conducts if gate0
• Hence complementary
• Basic gates
• Inverter, NAND, NOR

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Basic logic gates
F x y AND
F x ? y XOR
F x Driver
F x y OR
F (x y) NAND
F x Inverter
F (xy) NOR
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Combinational logic design
A) Problem description y is 1 if a is to 1, or
b and c are 1. z is 1 if b or c is to 1, but not
both, or if all are 1.
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Combinational components
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Sequential components
Q lsb - Content shifted - I stored in msb
Q 0 if clear1, I if load1 and
clock1, Q(previous) otherwise.
Q 0 if clear1, Q(prev)1 if count1 and
clock1.
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Sequential logic design
A) Problem Description You want to construct a
clock divider. Slow down your pre-existing clock
so that you output a 1 for every four clock cycles

• Given this implementation model
• Sequential logic design quickly reduces to
  combinational logic design

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Sequential logic design (cont.)
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HDL based design (review examples)

• D_Latch
• Greatest common divisor circuit (GCD)

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1-D_Latch VHDL module examples

• --D_latch.vhd
• library IEEE
• use IEEE.STD_LOGIC_1164.all
• ENTITY D_latch IS
• PORT ( d,clk IN STD_LOGIC
• q OUT STD_LOGIC)
• END D_latch
• ARCHITECTURE concurrent OF D_latch IS
• SIGNAL qwire,qb STD_LOGIC
• SIGNAL sb,rb,db STD_LOGIC
• BEGIN
• sb lt d nand clk rb lt not (d) nand
  clk
• qwire lt sb nand qb qb lt rb nand qwire
• qltqwire
• END concurrent

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1-D_Latch VHDL module examples

• ARCHITECTURE behaviour2 OF D_latch IS
• BEGIN
• Process (d,clk)
• variable qwire,qb STD_LOGIC
• variable sb,rb,db STD_LOGIC
• BEGIN
• if (clk'1') then qltd
• end if
• END Process
• END behaviour2
• - - test file (tD_latch.vhd)
• library IEEE
• use IEEE.STD_LOGIC_1164.all
• entity DlatchTB is
• end DlatchTB
• Architecture TB_arch of DlatchTB is

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2- Greatest common divisor circuit (GCD)

• continually subtracting the smaller of the two
  numbers, A or B, from the largest.
• Stop when the smallest 0
• file gcd_test_data.txt                  
•   21    49    7          
•   25    30    5          
•   19    27    1          
•   40    40   40    
•       
• file gcd_test_data_hex.txt                  
•   15    31    7          
•   19    1E    5          
•   19    27    1          
•   28    28   28   
•          

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Greatest common divisor circuit (GCD) C code

• include ltstdio.hgt
• main ()
•    int A_in, B_in, A, B, Swap, Y, Y_Ref
•    FILE file_pointer
•    file_pointer fopen("gcd_test_data.txt",
  "r")
•    while (!feof(file_pointer))          
•         fscanf (file_pointer, "d d d\n",
  A_in, B_in, Y_Ref)
•         A A_in B B_in
•         if (A ! 0 B ! 0)
•             while (B ! 0)
•                while (A gt B)
•                    A A - B
•                 
•                Swap A A BB Swap
•              
•           
•          else A 0
•         Y A //should be equal to Y_Ref

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Greatest common divisor circuit (GCD) Verilog
module

• module GCD_ALG(A_in,B_in,Y)
• parameter Width 8
• input Width-10 A_in, B_in
• output Width-10 Y
• reg Width-10 A, B, Swap, Y
• always _at_(A_in)// or B) begin
• begin
•      A A_in B B_in
•      if (A ! 0 B ! 0)
•        while (B ! 0) begin
•          while (A gt B) A A - B
• Swap A  A B   B Swap
•          end
•      else
•        A 0
• Y A
• end
• endmodule

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Greatest common divisor circuit (GCD) Verilog
module

• module test_GCD // Test GCD algorithm
• parameter GCD_tests 4
• parameter Width 8
• reg Width-10 A_in, B_in, Y_Ref
• integer N
• integer SimResults
• reg Width-10 AB_Y_Ref_Arr1GCD_tests3
• wire Width-10 Y
• GCD_ALG U0 (A_in,B_in,Y)
• initial monitor (" GCD Ad Bd Yd. Y
  should be d", A_in, B_in, Y, Y_Ref)
• initial begin
• readmemh("gcd_test_data_hex.txt",
  AB_Y_Ref_Arr)
• SimResults fopen("gcd_simres.txt") // Open
  simulation results file
• for (N0 NltGCD_tests NN1) begin
•    A_in AB_Y_Ref_Arr(N3)1
•    B_in AB_Y_Ref_Arr(N3)2

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Greatest common divisor circuit (GCD) VHDL module

• ENTITY GCD IS
• PORT
• ( A_in,B_in IN integer range 0 to 15
• Y OUT integer range 0 to 15
• )
• END GCD
• ARCHITECTURE behaviour OF GCD IS
• BEGIN
• Process (A_in,B_in)
• variable A, B, Swap integer range 0 to 15
• BEGIN
• A A_inB B_in
• for i in 0 to 15 loop
• if (A / 0 and B / 0) then
• if (AgtB) then
• A A - B
• else