ViSoC

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ViSoC

• Virus Identification System on Chip

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Design Goals

• A portable system capable of fast identification
  of viruses in places such as makeshift health
  centers for epidemic outbreak area
• Requirements
• Independent operation
• Ability to store own database
• Able to configure independently
• On system output display

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Design Goals

• Hold Virus Database on small non-volatile memory
  (Compact Flash)
• Run at least 2 modes of identification
• Enable on system configuration (Keypad or switch
  based configuration)
• On system, result display via LCD

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Non-volatile Memory

• Why Compact Flash?
• Power
• Use 3.3V or 5V operation
• Low power consumption
• lt5 power than that required for 1.8" and 2.5"
  disk drives
• Speed
• Robustness
• Operating shock rating of 2,000 Gs, which is
  equivalent to a 10-foot drop
• CompactFlash data is protected by built-in
  dynamic defect management and error correction
  technologies.

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Multiple mode of operation

• Have a fast identification mode
• Keep on flash a set of viruses recently detected
• Have mode to test this viruses first and return
  immediately upon certain confidence level of
  detection
• Have mode to run full comprehensive test

Virus Database
Recent Viruses
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Self Configurable

• Able to set what modes to run, fast mode or
  comprehensive mode
• Initial plan to use switches to set mode
• Further expansion using keypad for more refined
  configuration such as the level of accuracy
  needed when running in fast mode

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Output and Alert

• On system virus identification via LCD
• Multiple result can be displayed via scrolling
• Beep and LED flashing for dangerous viruses
• Keep log of viruses detected and write back onto
  flash

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Design 1
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Design 1

• DSP demodulates analog signal
• TinyARM is responsible for finding Amino Acid
  Sequence
• AVR interfaces with CF memory and Nios processor
• Nios processor runs Blastp Algorithm
• There is a double-buffer in between TinyARM and
  Nios Processor to facilitate data transfer
• Nios Processor sends result to LCD Display
• Simpler but slower

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Design 2
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Design 2 (Full custom Blast)

• DSP demodulates analog signal
• Fully-custom hardware on Nios processor - finding
  Amino acid sequence, neighbor word and word hits,
  extending word hits and finding best match
• Nios Processor sends result to LCD Display
• Fast, complex, and time consuming

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Design 3 (Final Design)
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Design 3 (Final Design)

• DSP demodulates analog signal
• DMA controller loads data from Compact Flash
  while Nios is doing computation in order to save
  time
• Custom hardware for finding Acid Amino and
  Neighbor Word
• Nios sends result to LCD Display
• Reasonable feasible design

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Design Comparisons
Scale of 1 to 5
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Exploration Plans

• Custom DMA for loading database in SRAM from
  Compact Flash
• -Feasiblity
• -Efficiency
• Reprofile Blast in C to determine parts to be
  implemented in custom hardware. Currently, string
  matching areas seem best done in custom hardware
• Research other communication between ARM and NIOS
  specifically SPI

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Implementation Plan

• CompactFlash
• C code for the ARM to interface with the
  CompactFlash
• Setting up storage format
• Getting our NIOS to communicate with the CF (
  through the ARM )
• Enable writing / reading / erasing of the card

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• DSP
• C code for the DSP to demodulate signals
• Test and debugging
• DSP -gt NIOS communications via 4 phase
  handshaking
• Custom Hardware
• Identify the extensively used calculations that
  takes the bulk of the time
• Direct Memory Access to our CF card from the NIOS
• Write Verilog, test download to FPGA

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Alert System

• Comparing of results to Most Wanted Viruses
• Display alerts to LCD screen and sound
• Saving a log of all results in CF card in
  files/database compatible to PC

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Verification, Integration Testing

• Generating input/output test vectors using MATLAB
  comparing with our C / Verilog output
• Integrating each component
• Ensure correctness of communication protocol
  between components

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Division of Labor

• Compact Flash, ARM lt-gt Nios
• Han Chun Lim (HC)
• NIOS software/ C programming
• Yong Khong Chong (YKC)
• Custom Hardware/ Verilog
• Robert Chu
• DSP, Memory Integration (DMA, SRAM, Avalon)
• Imran Sulaiman

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Schedule (part I)
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Schedule (part II)
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Plan for Demo 1

• Nucleotide to Protein Translation
• Custom Verilog on the NIOS board

...TCTCGATCTGGAC...
Custom Hardware (NIOS)
(01100110110001100111110010)
Binary representation for each Nucleotide
...TRSG ...
8bit Character for each Nucleotide Triplet
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More on Demo 1

• MATLAB to C code of BLASTP algorithm
• Verification of code
• Profiling of C code
• Optimization
• See what we can
• make custom HW

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The Flu
Common Cold
Ebola
Mono
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Rest of Virus, bacteria, etc

• http//www.thinkgeek.com/cubegoodies/toys/6708/ima
  ges/817/