Glitch-Free Design of Low Power ASICs Using Customized Resistive Feedthrough Cells

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Glitch-Free Design of Low Power ASICs Using
Customized Resistive Feedthrough Cells
Siri Uppalapati GDA Tech., Inc. San Jose, CA 95131, USA siri_at_gdatech.com Michael L. Bushnell Rutgers University Piscataway, NJ 08854, USA bushnell_at_caip.rutgers.edu Vishwani D. Agrawal Auburn University Auburn, AL 36849, USA vagrawal_at_eng.auburn.edu
9th VLSI Design Test Symposium VDAT
05 Bangalore, August 10-13, 2005
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Motivation

• Application Specific Integrated Circuit (ASIC)
  chips employ standard cell design style.
• Dynamic power consumed by glitches in a CMOS
  circuit, though significant, can be reduced or
  eliminated by design.
• Existing glitch reduction techniques demand
  customized gate design, not suitable for a
  standard cell ASIC.

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Power Dissipation in CMOS Logic (0.25µ)
Ptotal (0?1) CL VDD2 tscVDD Ipeak
VDDIleakage
CL
75
5
20
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Prior Work Hazard Filtering
Reference V. D. Agrawal, Low Power Design by
Hazard Filtering, VLSI Design 1997.

• Glitch is suppressed when the inertial delay of
  gate exceeds the differential input delay.

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or
1 or 3
2
Filtering Effect of a gate
2
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Prior Work A Reduced Constraint Set LP Model for
Glitch Removal
Reference T. Raja, V. D. Agrawal and M. L.
Bushnell, Minimum Dynamic Power CMOS Circuit
Design by a Reduced Constraint Set Linear
Program, VLSI Design 2003.

• Satisfy glitch suppression condition at all
  gates
• Differential path delay at gate input lt inertial
  delay
• Use a linear program (LP) to find delays
• Path enumeration avoided
• Reduced (linear) size of LP allows scalability
• Design gates with specified delays
• 40-60 dynamic power savings in custom design
• Procedure is not suitable for pre-designed cell
  libraries

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Prior Work ASIC

• J. M. Masgonty, S. Cserveny, C. Arm and P. D.
  Pfister, Low-Power Low-Voltage Standard Cell
  Libraries with a Limited Number of Cells, PATMOS
  01
• Transistor sizing results in 20 - 25 savings in
  power
• Power optimized by minimizing parasitic
  capacitances
• No glitch reduction attempted
• Y. Zhang, X. Hu and D. Z. Chen, Cell Selection
  from Technology Libraries for Minimizing Power,
  DAC 01
• Mixed Integer Linear Program (MILP) to select
  from different realizations of cells such that
  power consumption is minimized without violating
  delay constraints
• Sum of dynamic and leakage power is minimized
• Library contains cells of varying sizes, supply
  voltages, and threshold voltages
• Achieved 79 power saving on an average
• No glitch reduction attempted.

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New Glitch Removing Solution

• Balanced the differential delays at cell inputs
• Using delay elements called Resistive Feedthrough
  cells
• Automated the delay element
• Generation
• Insertion into the circuit

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Comparison of Delay Elements

• Resistor shows
• Maximum delay
• Minimum power and area per unit delay
• Hence, best delay element
• Resistive feed through cell
• A fictitious buffer at logic level

Delay element Average delay (ns) Delay/Power Delay/Area
I 0.28 0.22 .03
II 0.59 4.43 0.05
III 0.72 5.54 0.11
IV 0.63 1.05 0.16
III. Polysilicon resistor
I. Inverter pair
II. n diffusion capacitor
IV. Transmission gate
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Resistive Feedthrough Cell

• A parameterized cell
• Physical design is simple easily automated
• No routing layers(M2 to M5) used not an
  obstruction to the router

R?(length of poly)
R
Width of poly
S. Uppalapati, Low Power Design of Standard Cell
Digital VLSI Circuits, Masters Thesis, Rutgers
University, Dept. of ECE, Piscataway, NJ, Oct.
2004.
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RC Delay Model

• CL varies during transition (model not perfectly
  linear)
• Spectre simulation data stored as a 3D lookup
  table
• Average of signal rise and fall delays
• Linear interpolation used

TP
CL
R
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Design Optimization Flow
Design Entry
Find delays from LP
Find resistor values from lookup table
Tech. Mapping
Remove Glitches
Generate feed through cells and modify netlist
Layout
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Results
Circuit New Standard Cell Based Design New Standard Cell Based Design Power saved () in custom design Raja et al.
Circuit Area overhead () Power saved () Power saved () in custom design Raja et al.
4 bit ALU 29.5 23.7 N/A
c432 114.0 50.0 35.0
C499 86.0 32.0 29.0
C880 98.0 43.0 44.0
C1355 22.0 68.3 56.0
C2670 14.0 30.0 31.0
S. Uppalapati, Low Power Design of Standard Cell
Digital VLSI Circuits, Masters Thesis, Rutgers
University, Dept. of ECE, Piscataway, NJ, Oct.
2004.
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Glitch Elimination on net86 in 4bit ALU
Source Post layout simulation in SPECTRE
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Layouts of c880
Power saving 43 Area increase 98
Original layout of c880
Optimized layout of c880
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Conclusion

• Successfully devised a glitch removal method for
  the standard cell based design style
• Does not require redesign of the library cells
• Does not increase the critical path delay
• Modified design flow maintains the benefits of
  ASIC
• On an average
• Dynamic power saving 41
• Area overhead 60
• Possible ways to reduce area overhead
• Cell replacements from existing library
• On-the-fly-cell design
• Adjust routing delays for glitch suppression