EECoE 11602160 Embedded Systems Laboratory

1
EE/CoE 1160/2160Embedded Systems Laboratory

• Lab 3 Introduction to Signal Tap ELA

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Signal Tap Introduction

• ELA Embedded Logic Analyzer
• Custom built for your particular design
• DOES REQUIRE AREA ON THE FPGA

3
Getting Started

• Open Design In Quartus
• Compile design if not already compiled

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Open a New Signal Tap File
File -gt New -gt Other Files -gt SignalTap File -gt OK
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Set Clock
Click button next to clock name and use node
finder
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Gather Signals
Double Click Node Listing and use the Node Finder
to add signals
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Set Triggers
Enable Trigger for clear pin Set trigger
pattern Disable Trigger for other pins Select
Pre trigger position
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Set Hardware
Click Setup Click Add
Hardware Double Click
ByteBlasterII
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Compile and Program
Save Signaltap II file and then Compile Program
the FPGA board
10
Watch System
Press Play, Hit Clear button to trigger Signal
Tap.
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For Lab Today

• Use Old Design, but REMOVE the clock divider!
• Print-out Block Diagram, Simulation Results (can
  be old ones), and SignalTap Results
• Include ALL in report