Fred Chen, Dave Wang, Ben Coates, Ryan Tu,

1
Module Generation

• Fred Chen, Dave Wang, Ben Coates, Ryan Tu,
• Rhett Davis,
• Robert Brodersen
• June 16, 1999

2
Simulink Module Library

• Adders
• Subtractors
• Registers
• MUXs
• Adder/Subtractors
• MACs
• Multipliers
• Comparators

3
Module Design Considerations

• Key Design Conventions
• Naming Consistency With Higher Level (Simulink)
  Module Definitions
• Consistent Layout Conventions Between Modules
• Other Concerns
• Discrepancies Between Enable Lines In Standard
  Cells and Clock Signals in Simulink

4
Module Design Tradeoffs
Custom vs. General Design

• Custom Design
• Fewer More Rigid Leaf Cells (specific purpose)
• Better Performance / More Compact
• Less Flexible
• Not Easily Reused

• General Design
• More Numerous Generic Leaf Cells
• Greater Flexibility
• More Reusable For Future Designs
• Performance Area Sacrificed

5
Back End Design Flow
Simulink MDL File
TLC
(Stateflow blocks)
(Subsystems)
Makefile
MasterLibrary
Elaboration
Macro Cells
Modules
Pre-Layout Analysis Verification

• Leaf Cells
• Layout gen.
• Abs. gen.
• Schem. gen
• Elaboration Scripts

Layout
Launch PR
Post-Layout Analysis Verification
Stream Out
6
Generator Flow
User Input Leaf Cells
Generator Skill Code
Schematics
Layout
Module Characterization
Power Area Delay
Extraction Simulation
7
Module Design Example N-Bit Register
Start with Simulink library part
This specifies a register of n-bits

• This library part corresponds to
• Skill code to generate module
• A specific leaf cell

8
Skill code
Leaf cell
Skill code repeats leaf cell and indexes inputs
and output pin names as specified by simulink.
Finished module
9
Future Work

• Define More Concrete Translations From Simulink
  Models To Cadence Modules
• Define and Design Complex Modules (e.g. CORDIC
  or Complex Multiplier)
• Develop Module Characterization Procedure And
  Format
• Develop Comprehensive Module Libraries