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Design for Physical Debug for Silicon Microsurgery and ... Thong, 1993, Plenum Press. 3. Manufacturing Test vs. Debug. Test screens for manufacturing defects ... – PowerPoint PPT presentation

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Title: 1


1
Physical Debug
  • Manufacturing test, electrical debug, and
    physical debug
  • Scanning Electron Microscopy (SEM)
  • Electron-Beam Probing (E-Beam)
  • Picosecond Imaging Circuit Analysis (PICA)
  • Infrared Navigation with Fiducials
  • Laser Voltage Probing (LVP)
  • Focused Ion Beam (FIB) Editing
  • Spare Hardware for FIB ECOs
  • Micromechanical Probing

2
References
  • Design for Physical Debug for Silicon
    Microsurgery and Probing of Flip-Chip Packaged
    Integrated Circuits
  • Livengood Medeiros, ITC 99, p.877-882
  • Novel Optical Probing Technique for Flip-Chip
    Packaged Microprocessors
  • Paniccia, Eiles, et. al., ITC 98, pp. 740-747
  • Picosecond Imaging Circuit Analysis
  • Tsang et. al., IBM Journal of RD
  • www.research.ibm.com/journal/rd/444/tsang.html
  • Electron Beam Testing Technology
  • Thong, 1993, Plenum Press

3
Manufacturing Test vs. Debug
  • Test screens for manufacturing defects
  • Not all die are faulty (some known good die
    available)
  • Different die fail in different ways due to
    different defects
  • Debug searches for design validation escapes
    which affect all die
  • Functional design errors which escaped validation
  • Unexpectedly slow critical path missed by timing
    analysis
  • Other behaviors not correctly modeled by
    simulators
  • Goals of debug diagnosis work-around
  • Root-cause the failure to fix in next stepping
  • Peel the onion to debug multiple problems in
    one stepping

4
Electrical Debug
  • Controllability observability of 1s and 0s
  • Use DFT (design-for-test) hooks
  • Scan
  • Feature disable modes
  • Fault diagnosis
  • Identify set of all modeled faults
  • Use fault simulation to find which tests detect
    which faults
  • Given pass / fail status of a specimen for each
    test, intersect fault lists to diagnose the fault

T2
T1
Fault List
5
Physical Debug
  • Why physical debug?
  • Need to control or observe signal with no test
    point or scan cell
  • Need to observe analog behavior (delays, slopes)
  • Need to modify layout to fix a timing or
    functional bug
  • Use DFD (design-for-debug) hooks
  • Probe points
  • FIB cut and connection points
  • Working with transistors wires, not modeled
    faults

6
Scanning Electron Microscopy
  • Aim electron beam at object to be photographed
  • Secondary electrons reflected back from surface
  • Electrons collected analyzed with spectrometer
  • Synchronized raster produces image
  • Magnification 100x - 100,000x
  • Different materials have different absorption
    behavior
  • 3-D resolution due to reflection angles and
    blockages

7
SEM for Defect Diagnosis
8
SEM Voltage Contrast
  • Place e-beam over a chip connected to a tester
  • Metal with negative bias reflects more electrons
    and appears brighter
  • Metal with positive bias reflects fewer electrons
    and appears darker

9
Fault Diagnosis with SEM Diff
  • Diff known good image and bad image to find
    errors

10
E-Beam Probing
  • Focus electron beam on a single conductor instead
    of capturing a whole image
  • Run a test in a loop and take multiple samples to
    average out noise and construct a voltage
    waveform
  • Probe top metal layers directly
  • Aim beam between wires or through DFD probe holes
    to access lower metals
  • Possible to probe through insulators, but always
    target conductors

11
E-beam as Invasive Probe
  • Probing is normally non-invasive due to low
    electron count in beam relative to carrier count
    in circuit
  • Increase beam power to charge up a MOS gate for
    primitive controllability

12
The Packaging RevolutionFrom Wire-Bond to
Flip-Chip
  • Wire bond packages
  • Pads on die perimeter
  • Pads connected to package by wires
  • Die mounted face-up in package
  • Can see and probe top layer of metal
  • Access to lower layers between top wires and
    through holes
  • Flip-chip packages
  • Pads across entire die surface
  • Pads connected to package by solder balls
  • Die mounted face-down in package
  • Wires buried under silicon - too thick to e-beam
    through
  • Could drill holes through silicon to expose wires
  • Non-destructive probing technique is preferable

13
Electrons are OutInfrared Photons Are In
  • Carriers emit photons as they flow across P-N
    junctions
  • Materials and dopant concentrations are chosen in
    LEDs to make the photon wavelength in the visible
    spectrum
  • Normal MOSFETs emit infrared photons when they
    switch (no steady-state current flow)
  • Silicon is transparent to infrared light
  • IR photons pass through substrate, out the
    backside of the die
  • Focus an IR camera on the die to collect photons
  • Probability of emission is 1 in a million, so
    test needs to be run through millions of loops to
    collect enough photons

14
Picosecond Imaging Circuit Analysis (PICA)
15
Infrared Navigation with Fiducials
  • How do I know what Im looking at?
  • Frontside access Use top metal geography to get
    oriented
  • Backside access No way to tell whats under
    flat silicon
  • Place DFD fiducial beacons across the chip
  • Under IR camera, look like bright lights
    surrounded by darkness
  • Align a CAD overlay to locate hidden layout
    features

16
Laser Voltage Probing (LVP)
  • Probing version of IR microscopy
  • Analogous to e-beam
  • Reflected optical power is proportional to
    voltage across reverse-biased P-N junction
  • Place DFD probe-able diodes at gate inputs

17
Focused Ion Beam (FIB) Editing
  • Used for debug workarounds engineering samples
  • Not reliable enough for production
  • Physically modify a circuit
  • Break existing wires
  • Deposit tungsten to create new wires
  • Destroy repair to access buried wires
  • Cannibalization
  • Success rate throughput time metrics
  • DFD features to make FIB access easier
  • Deterministic opportunistic

18
Drilling Holes with FIB
19
Spare Hardware
  • Spare combinational and/or sequential cells
  • Need to choose types density requirements
  • Spare wires
  • Need to choose lengths, metal layers, and
    accessibility
  • Placement policy decisions
  • Add concurrently with functional design to
    guarantee availability?
  • Add in leftover space after design to minimize
    overhead?
  • How much spare hardware should be added?
  • Leave floating or tie to power rail?
  • DFD features for FIB accessibility, or ECO only?

20
Example Complex FIB Edit
21
SEM Photos of Edit
22
Micromechanical Probing
  • Touch 1-um probe to wire or contact point
  • Used to probe top metal directly when geometries
    were bigger
  • Now, probe FIB-deposited metal pads
  • Typically used for power clock, not signals
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