Fast Direct GPS Signal Acquisition Using FPGA

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Fast Direct GPS Signal Acquisition Using FPGA

• Jing Pang
• Janusz Starzyk

School of Electrical Engineering and Computer
Science Ohio University Athens, OH U. S. A.
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Outline

• Direct P-code Acquisition Overview
• GPS Background
• GPS signal structure
• Parallel code phase search for signal acquisition
• P-code Generator Architecture
• P-code Tuning Model
• P-code Property
• Noncircular convolution with zero padding
• Autocorrelation and acquisition margin
• Direct Average Method
• Design Platform, Design Flow and Hardware
  Architecture
• Summary

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Direct P-code Acquisition

• Time domain acquisition
• Massive physical parallel correlators
• FFT search
• Most of the reported approaches require large
  size FFT
• New approach
• Direct average
• Small size FFT for FPGA implementation

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GPS Signal Structure
Modulo-2 summation
Mixer
Summation
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GPS Receiver Acquisition
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Parallel Code Phase Search
FFT-based Circular Correlator
Digital IF
Code Generator
Y
N
Carrier Generator
peak detected ?
more freq. bins ?
N
Y
Failed
Acquired
Acquisition Result
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Circular Correlator
A?B
a ? b
a
A
FFT
IFFT
b
B
B
Conjugation
FFT
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GPS P-code Generator
Short cycle 4092, 4093 Held after 3749 short
cycles 7 Day Reset Extra 37 chips Generate
P-code Different satellites
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LFSR X1 And X2
X1B
X1A
X2B
X2A
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Epochs
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P-codes Reset Timing
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P-code Generator Tuning Model
z1a index to the X1A LFSR State at the
specified Time
x1a divide-by 3750 counter
y1a z-counter value
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P-code Property

• Circular convolution for periodic code
• Circular convolution with zero padding

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P-code Property

• Each satellite uses unique P-code to implement
  CDMA technique

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Acquisition Margin

• Mean value of acquisition margin 25.954
• Standard deviation 1.841
• Each acquisition margin value is obtained over 1
  ms

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Direct Average Method

• Direct average method is proposed due to the
  extremely long period of P-code
• Direct average over 128 samples autocorrelation
  result
• Summation of correlation results for 15 1-ms
  windows

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Direct Average Method

• Acquisition margin distribution over 1 s.
• The mean value of the acquisition margin 26.882
• The standard variation 2.676

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Design Platform

• Nallatech Board

PCs PCI interface
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Xilinx VirtexE Architecture

• Overall architecture
• One Slice of a CLB
• IOB
• GRM

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Design Flow
Design Entry
Functional Simulation Timing Simulation
User C Application
Design Synthesis
Nallatech DLL Software Interface Nallatech
Custom Hardware Interface
Mapping
Placement
Routing

VirtexE chip
Bit File
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FPGA Design Partition
Average
IFFT Processor
FFT Processor
GPS signal
Average
Local reference generation unit
Local Reference FFT Processor
NCO
Maximum selection Other control decision logic
Correlation peak peak location
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VirtexE FPGA Design Cost

• 1. NCO 2. P-code generator 3. Average
  4. FFT 5. IFFT 6. Complex conjugate
  multiplication
• 7. Correlation amplitude square
• 8. Peak selection and decision logic
• Total available CLB slices 15552
• Total available Block Rams 144

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Summary

• Flexible GPS P-code generator tuning model
• Produce P-code starting from any time of a GPS
  week
• Direct Average Method
• Improve acquisition speed
• Simplify FPGA hardware design
• Hardware FPGA implementation