Rapid Estimation of Control Delay from High Level Specifications

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Rapid Estimation of Control Delay from High Level
Specifications
Gagan Raj Gupta, University of Wisconsin -
Madison Madhur Gupta, Purdue University Preeti
Ranjan Panda, Indian Institute of Technology Delhi

• 43rd Design Automation Conference
• 24-28 July 2006, San Francisco, USA

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Output of Behavioural Synthesis
Datapath
Control
R1
R2
FSM State Reg
FSM Comb. Logic

Control signals
S
R3
Status signals
3
Critical Path Involves bothFSM and Datapath
R1
R2
FSM State Reg
FF Prop Delay
FSM Comb. Logic
FSM Delay
MUX Delay
Clock Period
FU Delay

MUX Delay
FF Setup Time
R3
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Circular Problem

• Effective clock period for Scheduling
• need to subtract control delay
• Circular problem
• FSM is determined only after scheduling
• Too late to modify schedule
• This would change the FSM
• FSM delays may invalidate schedule
• FSM delay may be large
• Problem We would like to estimate control delay
• From high-level information
• Without synthesising the FSM

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Previous Work

• Control area estimation
• ASIC (Mitra DT93)
• FPGA (Menn ISSS02, Nayak DATE02)
• Exact handling
• Include Logic Synthesis Timing (Bergamaschi
  TCAD02)
• Fix Datapath Template (Reshadi ISSS05)
• Ignores possible optimisations in logic synthesis
• Synopsys Behavioral/SystemC Compiler
• Designer gives estimate of control delay
• Difficult to provide

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Overall Strategy
SpecificationGenerator
HLS
Behavioral Parameters
Datapath FSM
Behavioral C Description
Control Synthesis
Gate Level Netlist

• Empirical formulas drawn from experiments
• Plot delays for different parameters
• fit curves

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Factors Affecting Control DelayNumber of
Operations

• More operations gt higher controller complexity
• Delay varies logarithmically

Delay A log( of operations)
RMS Error 9.3
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Factors Affecting Control DelayState Register
Width

• DelayAlog( operations)( of state bits)
• Staircase pattern
• Number of state bits (binary encoding)

RMS Error 10.3
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Factors Affecting Control DelayResource
Constraint/Schedule Length

• DelayAlog( of operations)( of state bits)
• Increase resources
• Schedule length decreases
• Smaller delays

5 Resources
RMS Error 10.3
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Factors Affecting Control DelayMulti-cycle
Operations

• Resources with different latencies do they
  affect the controller differently?
• Experimental observation NO, same formulation
  suffices
• Effect of latency already captured in states

Mixed Latencies 20 - 80
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Factors Affecting Control DelayNumber of
Variables

• More global varsgtmore registers, more control
• Local vars gtsharing possible
• Experiment resources constant and varying vars
• Curve fit to find co-efficient A

20 variables, 5 adders, 5 multipliers
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Factors Affecting Control DelayNumber of
Resources

• Resource constraint R vs degree of parallelism P
• P ? R gt some resources never used, no impact on
  controller
• P gt R ? sharing, MUX control from FSM
• Curve fit to find A

20 variables, 8 adders, 8 multipliers
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Other Factors Affecting Control Delay

• Number of Basic Blocks
• Behavioural constructs (if, switch, loop) lead to
  increased basic blocks, which affect FSM
  structure
• Experiments
• varying conditionals
• varying loop nesting depths
• RESULT no significant difference
• Indirectly affects schedule length, which IS
  considered
• Designs with Memory
• Control complexity does NOT depend on size
• Only on number of memories
• Treated as just another resource

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Overall Formulation

• Count the number of nodes in the CDFG
• Estimate the number of states by performingan
  approximate list schedule
• Ax y ? ( FU control bits) z ? ( variables)
• x, y, z specific to the library
• Delay A ? log( operations) ? ( state bits)

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Validation
7000
Estimation
6000
Actual
5000
4000
Delay in p.s.
3000
2000
1000
0
FIBO
FACT
EPIC
GCD
Bubble
JIDCT
JFDCT
CRC32
New-life
Histogram
Blowfish
ADPCM
Avg. Error 6.9
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Conclusion

• Technique to estimate control delay from
  behavioural specification
• without detailed synthesis
• average 6.7 error
• leads to more accurate scheduling
• Fast estimate useful in design space exploration