Computer System Basics Introduction

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Computer System BasicsIntroduction

• Lynn Choi
• Dept. Of Computer and Electronics Engineering

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Digital Computer

• Binary numbers
• All the Information in a digital system is
  represented as binary numbers
• A binary digit is called a bit (b)
• Information is represented in group of bits
• A group of 8 bits is called a byte (B)
• 210 as K (Kilo), 220 as M (Mega) 230 as G
  (Giga) 240 as T (Tera)

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Information Representation

• Digital information
• Program (code)
• A sequence of instructions
• Instruction contains opcode and operands
• Data
• Text (alphanumeric codes)
• ASCII (7b) Stored in a byte (0 is padded to
  MSB)
• Unicode (16b)
• Numbers
• Integer unsigned, sign-magnitude, 2s complement
• Floating point sign-significand-exponent
• Logical data n 1-bit Boolean data
• Address the location of memory (data or
  instruction address)
• Multimedia
• Image 1024 x 768 pixels (1b 3B per pixel)
• Video, audio MPEG

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Alphanumeric Codes

• Handle text of letters and numbers
• Set of elements include 10 digits, 26 letters,
  special characters
• 36 64 letters if only capital letters need 6
  bits
• 64 128 letters if upper/lower letters need
  7 bits
• ASCII character code
• American standard code for information exchange
• Standard binary code is ASCII (table 1.4)
• ASCII contain 94 printable chars 34 control
  chars
• Unicode
• A new standard for 16-bit (2 byte) alphanumeric
  codes
• Referred to as Unicode/10646
• 16 bits provide 65,536 code words,
• Represent the symbols and ideographs of the
  world's languages

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Advances in Intel Microprocessors
80
81.3 (projected)
Pentium IV 2.8GHz (superscalar, out-of-order)
70
60
45.2 (projected)
Pentium IV 1.7GHz (superscalar, out-of-order)
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SPECInt95 Performance
40
24
Pentium III 600MHz (superscalar, out-of-order)
30
8.09
11.6
PPro 200MHz (superscalar, out-of-order)
20
3.33
Pentium 100MHz (superscalar, in-order)
Pentium II 300MHz (superscalar, out-of-order)
1
80486 DX2 66MHz (pipelined)
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1992 1993 1994 1995 1996
1997 1998 1999 2000
2002
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Instruction Set Architecture

• ISA Instruction Set Architecture
• Defines
• Machine instructions
• Visible machine states
• Registers
• Memory
• Examples
• X86(IA-32)
• 386 Pentium III, Pentium IV
• IA64
• Itanium, Itanium2
• PowerPC
• SPARC
• MIPS
• ARM

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Basics What is a Computer?

• The computer is a complex sequential circuit
• States
• Memory and registers
• Consists of static and dynamic RAMS
• SRAM latches, flip-flops, registers, buffers,
  caches
• DRAM main memory
• Inputs
• Programs a sequence of instructions
• Each instruction causes a state transition
• ADD R3 lt- R1, R2
• Data
• Outputs
• Printed materials, images, video streams, sounds,
  packets
• Include all sorts of combinational/sequential
  circuits
• Decoders, Adders, Multipliers, Shifters,
  Encoders, etc.

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Basics What is inside Computer?

• Processor(s) also called CPU (Central Processing
  Unit)
• Fetches instructions from memory
• Executes instructions
• Transfers data from/to memory
• Memory caches, main memory, HDD, ROM, FLASH, ..
• Stores program and data
• Input devices
• Mouse, keyboard, camera, pen, touch screen,
  barcode reader, scanner, microphone,
• Output devices
• Printer, monitor, speaker, beam projector, ..
• Interconnects buses
• Motherboards, chipsets,

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Terminology

• Microprocessor a single chip processor
• Pentium IV, AMD Athlon, SUN Ultrasparc, ARM,
  MIPS, ..
• ISA (Instruction Set Architecture)
• Defines machine instructions and visible machine
  states such as registers and memory
• Examples
• X86(IA32) 386 Pentium III, Pentium IV
• IA64 Itanium, Itanium2
• Others PowerPC, SPARC, MIPS, ARM
• Micro-architecture
• Implementation implement according to the ISA
• Pipelining, caches, branch prediction, buffers
• Invisible to programmers

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Terminology

• CISC (Complex Instruction Set Computer)
• Each instruction is complex
• Instructions of different sizes, many instruction
  formats, allow computations on memory data,
• A large number of instructions in ISA
• Architectures until mid 80s
• Examples x86, VAX
• RISC (Reduced Instruction Set Computer)
• Each instruction is simple
• Fixed size instructions, only a few instruction
  formats
• A small number of instructions in ISA
• Load-store architectures
• Computations are allowed only on registers
• Data must be transferred to registers before
  computation
• Most architectures built since 80s
• Examples MIPS, ARM, PowerPC, Alpha, SPARC, IA64,
  PA-RISC, etc.

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Terminology

• Word
• Default data size for computation
• Size of a GPR ALU data path depends on the word
  size
• The word size determines if a processor is a 8b,
  16b, 32b, or 64b processor
• Address (or pointer)
• Points to a location in memory
• Each address points to a byte (byte addressable)
• If you have a 32b address, you can address 232
  bytes 4GB
• If you have a 256MB memory, you need at least 28
  bit address since 228 256MB
• Caches
• Faster but smaller memory close to processor
• Fast since they are built using SRAMs, but more
  expensive

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Terminology Memory

• Volatile vs Non-volatile
• Non-volatile memory
• A memory that can retain its state without power
• ROM, PROM, EPROM, EEPROM
• Read-only or write time much greater than read
  time
• FLASH, DISK, TAPE
• Volatile memory
• A memory that cannot retain its state without
  power
• SRAM, DRAM
• Random-access vs serial access
• Random acess
• Access time is independent of the location of
  data
• RAM, ROM, FLASH
• Serial access memory- DISK, TAPE

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Terminology Memory

• Static vs. Dynamic Memory
• Static RAM (at least 6 transistor)
• State can be retained while power is supplied
• Use latched storage
• At least 6 transistors per bit
• Speed access time 8-16X faster than DRAM
• Dynamic RAM (usually 1 transistor)
• State is discharged as time goes by
• Use dynamic storage of charge on a capacitor
• A single transistor cell
• Require refresh of each cell every few
  milliseconds
• Density 8-16X SRAM size at the same feature size
• Multiplexed address lines - RAS, CAS
• Complex interface logic due to refresh, precharge

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SRAM Cell versus DRAM Cell
DRAM Cell
SRAM Cell
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Pentium IV Die Photo Whats inside a CPU?
Pentium 4 Processor Die on 0.18 micron (42M
transistors)
400MHz system bus
Advanced Transfer Cache
Pipeline
Trace cache
FP/MMX
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Todays Microprocessor

• Intel Pentium IV Processor
• Technology
• 0.13? process, 55M transistors, 82W
• 3.2 GHz, 478pin Flip-Chip PGA2
• Performance
• 1221 Ispec, 1252 Fspec on SPEC 2000
• Relative performance to SUN 300MHz Ultrasparc
  (100)
• 40 higher clock rate, 1020 lower IPC compared
  to P III
• Pipeline
• 20-stage out-of-order (OOO) pipeline,
  hyperthreading
• 2 ALUs run at 6.4GHz
• Cache hierarchy
• 12K micro-op trace cache/8 KB on-chip D cache
• On-chip 512KB L2 ATC (Advanced Transfer Cache)
• Optional on-die 2MB L3 Cache
• 800MHz system bus, 6.4GB/s bandwidth
• Compared with 1.06GB/s on P III 133MHz bus
• Implemented by quad-pumping on 200MHz system bus

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Processor Performance

• Texe (Execution time per program)
• NI CPIexecution Tcycle
• NI of instructions / program (program size)
• Small program is better
• CPI clock cycles / instruction
• Small CPI is better. In other words, higher IPC
  is better
• Tcycle clock cycle time
• Small clock cycle time is better. In other words,
  higher clock speed is better

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Anatomy of PC (PII, PIII)
CPU
L2
BSB
Host Bus
FSB
AGP
Host to PCI Bridge
Main Memory
Graphics
100 MHz SDRAM
(800MB/s)
PCI Bus
440BX AGPset
PCI to USB Bridge
Disks
LAN
USB
Sound
Keyboard/Mouse
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Memory Hierarchy Evolution
CPU
CPU
CPU
CPU
L1
I
D
I
D
L2
Cache
L2
L2
Chipset
Chipset
Chipset
Chipset
DRAM
DRAM
DRAM
DRAM
ISA
PCI
PCI
PCI
Pentium
386
486
P6 / P III
Cache - Write Through - Direct-Mapped FP DRAM
On-chip L1 - Write Through Off-Chip L2 -
Write Back - Direct-Mapped
Split L1 - Write Back L2 - Write Back -
Direct-Mapped EDO DRAM
Split L1 - WB, Write Allocate Backside
Bus On-package L2 - Non-blocking - 4 way
associative EDO/SDRAM
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Exercises Discussion

• 3.2GHz Pentium4 processor is reported to have
  SPECint ratio of 1221 and SPECfp ratio of 1252 in
  SPEC2000 benchmarks. What does this mean?
• How much memory can you address using 36 bits of
  address assuming byte-adderessability?
• Classify Intels 32bit microprocessors in terms
  of processor generations from 80386 to Pentium 4.
  Whats the meaning of generation here?
• Assume two processors, one RISC and one CISC
  implemented at the same clock speed and the same
  IPC. Which one performs better?