Instruction Set Architectures

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Instruction Set Architectures
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Instruction Operations

• Arithmetic and Logical
• add, subtract, and , or, etc.
• Data transfer
• Load, Store, etc.
• Control
• Jump, branch, call, return, trap, etc.
• Synchronization
• Test Set.
• String
• string move, compare, search.

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Instruction Usage Example Top 10 Intel X86
Instructions
Rank
Integer Average Percent total executed
1
2
3
4
5
6
7
8
9
10
Observation Simple instructions dominate
instruction usage frequency.
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Instructions for Control Flow
Breakdown of control flow instructions into three
classes calls or returns, jumps and conditional
branches for SPEC CPU2000 programs.
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Conditional Branch Distance

• Short displacement fields often sufficient for
  branch

FP Average
Integer Average
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Conditional Branch Addressing

• PC-relative, since most branches from current PC
  address
• At least 8 bits.
• Compare Equal/Not Equal most important for
  integer programs.

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Data Type and Size of Operands

• Byte, half word (16 bits), word (32 bits), double
  word (64 bits).
• Arithmetic
• Decimal 4bit per digit.
• Integers 2s complement
• Floating-point IEEE standard-- single, double,
  extended precision.

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Type and Size of Operands
Distribution of data accesses by size for SPEC
CPU2000 benchmark programs
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Instruction Set Encoding

• Considerations affecting instruction set
  encoding
• To have as many registers and address modes as
  possible.
• The Impact of the size of the register and
  addressing mode fields on the average instruction
  size and on the average program.
• To encode instructions into lengths that will be
  easy to handle in the implementation. On a
  minimum to be a multiple of bytes.

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Instruction Format

• Fixed
• Operation, address specifier 1, address specifier
  2, address specifier 3.
• MIPS, SPARC, Power PC.
• Variable
• Operation of operands, address specifier1, ,
  specifier n.
• VAX
• Hybrid
• Intel x86
• operation, address specifier, address field.
• Operation, address specifier 1, address specifier
  2, address field.
• Operation, address field, address specifier 1,
  address specifier 2.
• Summary
• If code size is most important, use variable
  format.
• If performance is most important, use fixed
  format.

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Three Examples of Instruction Set Encoding
Operations no of operands
Address specifier 1
Address field 1
Address specifier n
Address field n

Variable VAX (1-53 bytes)
Operation
Address field 1
Address field 2
Address field3
Fixed DLX, MIPS, PowerPC, SPARC
Operation
Address field
Address Specifier
Address Specifier 1
Address Specifier 2
Operation
Address field
Address Specifier
Address field 2
Operation
Address field 1
Hybrid IBM 360/370, Intel 80x86
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Summary ISA

• Use general purpose registers with a load-store
  architecture.
• Support these addressing modes displacement,
  immediate, register indirect.
• Support these simple instructions load, store,
  add, subtract, move register, shift, compare
  equal, compare not equal, branch, jump, call,
  return.
• Support these data size 8-,16-,32-bit integer,
  IEEE FP standard.
• Provide at least 16 general purpose registers
  plus separate FP registers and aim for a minimal
  instruction set.

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Complex Instruction Set Computer (CISC)

• Emphasizes doing more with each instruction
• Motivated by the high cost of memory and hard
  disk capacity when original CISC architectures
  were proposed
• When M6800 was introduced 16K RAM 500, 40M
  hard disk 55, 000
• When MC68000 was introduced 64K RAM 200, 10M
  HD 5,000
• Original CISC architectures evolved with faster
  more complex CPU designs but backward instruction
  set compatibility had to be maintained.
• Wide variety of addressing modes
• 14 in MC68000, 25 in MC68020
• A number instruction modes for the location and
  number of operands
• The VAX has 0- through 3-address instructions.
• Variable-length instruction encoding.

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Example CISC ISA Intel X86,386/486/Pentium

• Operand sizes
• Can be 8, 16, 32, 48, 64, or 80 bits long.
• Also supports string operations.
• Instruction Encoding
• The smallest instruction is one byte.
• The longest instruction is 12 bytes long.
• The first bytes generally contain the opcode,
  mode specifiers, and register fields.
• The remainder bytes are for address displacement
  and immediate data.

• 12 addressing modes
• Register.
• Immediate.
• Direct.
• Base.
• Base Displacement.
• Index Displacement.
• Scaled Index Displacement.
• Based Index.
• Based Scaled Index.
• Based Index Displacement.
• Based Scaled Index Displacement.
• Relative.

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Reduced Instruction Set Computer (RISC)

• Focuses on reducing the number and complexity of
  instructions of the machine.
• Reduced CPI. Goal At least one instruction per
  clock cycle.
• Designed with pipelining in mind.
• Fixed-length instruction encoding.
• Only load and store instructions access memory.
• Simplified addressing modes.
• Usually limited to immediate, register indirect,
  register displacement, indexed.
• Delayed loads and branches.
• Instruction pre-fetch and speculative execution.

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Reduced Instruction Set Computer (RISC)

• Reduced Instruction Set Computer (RISC)
• Simple instructions with regular formats
• Key Idea make the common case fast!
• infrequent operations can be synthesized using
  multiple instructions
• Assumes compiler will do optimizations
• e.g., scalar optimization, register allocation,
  scheduling, etc.
• ISA designed for compilers, not assembly language
  programmers
• Examples MIPS, SPARC, PowerPC, Alpha

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Example RISC ISA PowerPC

• Operand sizes
• Four operand sizes 1, 2, 4 or 8 bytes.
• Instruction Encoding
• Instruction set has 15 different formats with
  many minor variations.
• All are 32 bits in length.

• 8 addressing modes
• Register direct.
• Immediate.
• Register indirect.
• Register indirect with immediate index (loads and
  stores).
• Register indirect with register index (loads and
  stores).
• Absolute (jumps).
• Link register indirect (calls).
• Count register indirect (branches).

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Example RISC ISA HP Precision
Architecture, HP-PA

• Operand sizes
• Five operand sizes ranging in powers of two from
  1 to 16 bytes.
• Instruction Encoding
• Instruction set has 12 different formats.
• All are 32 bits in length.

• 7 addressing modes
• Register
• Immediate
• Base with displacement
• Base with scaled index and displacement
• Predecrement
• Postincrement
• PC-relative

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Example RISC ISA
SPARC

• Operand sizes
• Four operand sizes 1, 2, 4 or 8 bytes.
• Instruction Encoding
• Instruction set has 3 basic instruction formats
  with 3 minor variations.
• All are 32 bits in length.

• 5 addressing modes
• Register indirect with immediate displacement.
• Register inderect indexed by another register.
• Register direct.
• Immediate.
• PC relative.

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Example RISC ISA Compaq Alpha AXP

• 4 addressing modes
• Register direct.
• Immediate.
• Register indirect with displacement.
• PC-relative.

• Operand sizes
• Four operand sizes 1, 2, 4 or 8 bytes.
• Instruction Encoding
• Instruction set has 7 different formats.
• All are 32 bits in length.