The System Board Chapter 5

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The System BoardChapter 5

• David Turton
• Conestoga College
• Institute of Technology Advanced Learning
• http//www.conestogac.on.ca/dturton
• Doon 1D17 x3610

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Motherboard Determines

• CPU
• Types, speeds, number
• Chip set
• Expansion slots
• Type, number
• ROM BIOS
• Type and max memory
• RIMMs, DIMMs, SIMMs
• DDR, DDR2
• System bus speeds

• Drive controllers
• EIDE, SATA, SCSI
• Type of case
• Power supply requirements
• On-board ports
• Serial, parallel, USB, firewire
• Embedded components
• Network, video, sound, modem

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Embedded Components

• Components built onto motherboard
• Normally separate expansion cards
• Combination costs less than both separate
• Usually configured thorough CMOS
• Proprietary boards (599 computer with monitor)
• Are there any expansion slots?
• Can you disable onboard components?
• Can you use 3rd party components?
• Eg more powerful video card

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AT Form Factor System Board older computers
CPU interferes with long expansion cards
12"x13" baby AT 12"x8.5"
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ATX System Board - P II, P III- CPU located out
of way of expansion cards- IDE connectors near
drive bays- single vent fan in power supply, -
CPU fan pushes air from inside case
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NLX form factor for low-rise cases- expansion
cards disk controllers on riser card- second
external fan blowing directly at CPU
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BTX MicroBTX, PicoBTX- smaller size, improved
air flow, fewer expansion slots - powered air
duct around CPU's heat sink draws outside air
Note PCI express x1, x16
Note 2 pair memory slots DDR2?
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The CPU(32-bit single core)

• I/O unit
• Manages Data instructions entering/ leaving CPU
• Control unit
• Manages all activities inside CPU
• ALU (arithmetic logic unit 2 on Pentium CPU)
• Does all comparisons calculations
• Registers
• Hold data being worked on
• Cache memory
• Data instructions waiting to be worked on
• Back-side bus to cache runs at CPU speed
• 32-bit processors Pentiums, Athlons
• Processes 32 bits at a time, internally
• 64-bit front-side (external) bus to memory

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Attributes for Rating CPUs

• CPU speed
• 3.5 GHz (gigahertz) internally (3,500,000,000
  beats per second)
• Word size (internal data path)
• 32 or 64 bits
• bits processed per instruction
• Data path external bus
• 64 or 128 bits
• bits transported to CPU
• Instruction set built-in code
• MMX, SSE, Hyper Threading, Hyper Transport, etc.
• System bus speeds supported
• 1066, 800, 533, 400MHz

• Cache memory
• L1 internal to CPU chip
• runs at CPU speeds
• L2 usually external to chip
• usually runs at half CPU speed
• L3 further away than L2
• Still in CPU housing
• Multiprocessing
• 2 processors on one chip
• Intel in a year or two
• AMD now
• processors designed for 2 CPUs on motherboard

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Cache Memory(aka SRAM)

• SRAM Static RAM
• Holds data as long as has power
• Doesn't need continual refreshing like DRAM
• Faster than DRAM (main memory)
• Level 1 (L1) cache
• On the CPU die, part of its chip
• As fast as the CPU
• Execution Trace Cache
• Decoded instructions ready for execution
• Level 2 (L2) cache
• Off chip (usually), in same housing
• Advance Transfer Cache L2 cache on CPU chip
• Usually half speed of CPU
• 128K, 256K, 512K, 1MB

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Pentium III

• Slot or socket
• 100- or 133-MHz memory bus with a processor speed
  to 1.33GHz
• Introduced Intels SSE instruction set
• improves multimedia processing even further than
  MMX, once s/w catches up
• SSE Streaming Single-instruction, multiple-data
  Extension
• Pentium III Xeon
• High-end PIII for servers

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Pentium 4

• Processor speeds to 3.8GHz
• 400, 533, 800MHz FSB
• Improved multimedia over P III
• Later P4's
• Hyper-Threading Technology
• "Execute 2 threads in parallel"

• P4 Extreme Edition
• HT technology
• 1066MHz FSB
• Latest memory (DDR2)

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Mobile Pentiums

• Pentium M
• 2.1GHz on 400MHz FSB
• For Intel Centrino Technology
• Integrated CPU, chipset, wireless
• Mobile Pentium 4
• 3.46GHz on 533MHz FSB
• Features
• Low voltage less heat, less power

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32-bit AMDthe major Intel competitor

• AMD Sempron 2.0GHz/333MHz competing w/Celeron
• Mobile CPU's
• Mobile AMD Sempron, Mobile AMD Duron, Athlon XP-M

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64-bit Processors- need a 64-bit O/S and 64-bit
apps to take advantage- all will run current
32-bit applications- front-side bus (FSB) is 128
bits wide

• Intel
• Explicitly Parallel Instruction Computing (EPIC)
• Instructions to execute 2 instructions in
  parallel
• Itanium
• 800 MHz CPU, 266 MHz FSB, up to 4MB cache (L3)
• Itanium2
• 1.6 GHz CPU, 400/533 MHz FSB, to 9MB cache (L3)
• AMD
• First out with dual-core 64-bit processors
• Opteron servers workstations
• 2.6 GHz CPU, 800-1,000 MHz HT, 1MB L2 cache_at_CPU
  speed
• Athlon 64 desktops notebooks
• 2.6 GHZ CPU, 400MHz FSB, 1MB cache (L2)
• X2 dual-core
• FX gaming
• Turion 64 Mobile notebooks
• To 2.0 GHz CPU, 400 MHz FSB, 1MB cache (L2)

- HyperTransport I/O communication (system
bus) at 1,600Mhz
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RISC Technology

• RISC (reduced instruction set) vs CISC (complex
  instruction set)
• Chip interpreter decodes CISC instructions to
  RISC
• CPU is limited to a very few instructions
• Each instruction can execute in a single clock
  cycle
• Can process much faster when few complex
  calculations are required
• Ideal for video or telecommunications
  applications
• Easier and cheaper to manufacture

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CPU Heat Sinks Cooling Fans

• Maintain temperature at 32C to 43C
• heat causes system errors cuts CPU life
• Need thermal cream between heat sink CPU
• Copper heat sinks
• Better conductor
• Fan can be 25 slower (quieter)
• Can install heat alarm
• Also
• Peltier
• Refrigeration
• Water cooling

Fan connects to motherboard
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CPU Voltage Regulator(built onto motherboard)

• Controls the amount of voltage on the system
  board
• Dual voltage CPU
• Requires two different voltages, one for internal
  processing and the other for I/O processing
• Single voltage CPUs
• Requires one voltage for both internal and I/O
  operations
• Older boards are set by jumpers
• newer ones auto-sense

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CPU Voltage Regulator
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Chip Set

• Chips on the system board to control
• memory cache
• external buses
• some peripherals
• Intel dominates the chip market
• more compatible with Pentium CPUs
• Huge investment in RD to invent
• PCI bus
• Universal serial bus
• Advanced graphics port (AGP)
• Accelerated Hub Architecture
• See book for motherboards/chip sets/features

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Intel Chip Sets

• 400 series
• Uses the PCI bus as the interconnection between
  slower buses and the system bus
• i800 series
• Up to 4GB on DDR's
• Early ones supported RIMMs or DDRSDR DIMMs
• Introduced Accelerated Hub Architecture
• slower South Bridge reporting through faster
  North Bridge
• i900 series
• Supports DDR2, up to 1066 MHz bus, P4 extreme

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i800 Chip Set Architecture
PCI bus is ¼ to ½ memory bus AGP can be 4x memory
bus
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Buses and Expansion Slots

• Earliest PC
• Had only a single and simple bus (8-bit ISA bus)
• CPU, system/expansion bus 4.77MHz
• Todays PCs
• Have four or five buses, each with different
  speeds, access methods, and protocols
• Main bus between CPU memory is known as system
  bus, memory bus, front-side bus
• all other buses must interface with this

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What's a bus?

• What are they?
• Sets of lines on motherboard
• Carry data to components
• Usually parallel buses
• Data path carries 16, 32 or 64 bits at once
• Some are serial, like USB
• Data path carries 1 bit at a time (1 pair of
  lines)
• What does it do?
• Carries electrical power
• Carries control signals that coordinate all
  activity
• Passes memory addresses from one component to
  another
• Passes data

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PCI Express 64-bit local bus up to 16 "lanes",
each carrying 4GB each way _at_2.5 to 40 GB/s PCI
Express X1 to X16 allows device-to-device
communication, rather than through CPU PCI
Express X16 will replace AGP
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Bus Evolution

• Capacity is rated by data path size and speed
• PCI 32 bits 4 bytes 66MHz 264 MB/s
• Local buses (system buses)
• Work in sync with the CPU and the system clock
• Example memory bus, PCI, AGP, VESA buses
• Expansion buses
• Work asynchronously with the CPU
• At a much slower rate
• Example ISA bus, USB

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Why So Many Buses?

• Speeds of different hardware components evolve at
  different rates
• ISA cannot handle 100Mb/s for networking
• PCI barely handles Gigabit networking
• Single speed for all components is no longer
  practical
• Why build a modem to CPU speeds?
• CPU dumps to bus controller
• CPU stays at top pace
• controller buffers and writes to devices at
  slower speed

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Bus Connections on Expansion Cards
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Expansion Buses(not synchronised with the CPU -
i.e. not local buses

• ISA bus
• 8-/16-bit industry standard architecture bus used
  on the original 8088 PC
• EISA (extended ISA) bus
• 32-bit bus that can transfer 4 bytes a a time at
  a speed of about 20 MHz

continued
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Universal Serial Bus (USB)Expansion (unsync'd)
bus

• Designed to make installation and configuration
  of I/O devices easy
• Up to 127 devices daisy-chained together
• USB 1.1 12Mb/s
• USB 2.0 480Mb/s
• Single set of resources for all devices on the
  bus
• chipset controller polls each device
• 2 pairs of contacts
• Power
• 5v, max 500mA each connection
• Data
• Serial communications 1 bit at a time

Type A upstream
Type B downstream
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USB Enumeration
1 type B in, 4 type A out

• CPU queries each USB device
• Assigns each one an address
• Determines type of transfer (dedicated slots per
  packet)
• Interrupt like a keyboard, 1 byte at a time
• Bulk 64-byte packets, like to a printer
• Isochronous real-time streaming, like a speaker
• Adding ports
• USB hub (above)
• To add ports max 5M cable length, max 6 cables
  away
• Un-powered hubs must have self-powered devices
• USB expansion card (PCI slot)

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USB Portscurrent systems have 6-8 4 as jacks, 2
as connection for USB ports on case.
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FireWire or IEEE 1394

• Preceded USB, designed by Apple
• Serial, like USB
• up to 63 devices
• Faster 400Mb/s vs USBs 12Mb/s (at the time)
• Intended for high throughput devices
• network cards, camcorders, DVD, and other
  high-speed, high-volume devices

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Local I/O BusesLocal - synchronised with the
memory bus

• Fast access to the CPU by way of the memory bus
• VESA (Video Electronics Standards Association) VL
  bus (replaced by the PCI bus)
• Used on 80486 computers for connecting 32-bit
  adapters directly the the local processor bus
• PCI (peripheral component interconnect) bus
• Common on Pentium RISC computers
• 33 or 66 MHz, with a 32-bit data path
• PCI bus is middleman to expansion buses

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PCI Bus
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Accelerated Graphics Port (AGP)32-bit slot on a
system board for a video cardruns at same speed
as memory bus - faster than PCIDIME direct
memory execute can share system memory, to avoid
copying to video memory
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Audio Modem Riser (AMR)

• A slot to accommodate a small modem card or sound
  card
• Adds the card at a low cost
• without using up a PCI or ISA slot
• Passing phase?
• Sound now built onto motherboard
• Modems fading away

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Hardware Configuration

• Communicates to the CPU what hardware components
  are present in the system and how they are set up
  to interface with the CPU
• Provided on system board in three ways
• DIP switches
• Jumpers
• CMOS
• power supplied by battery retains data even when
  computer is turned off
• configured by a BIOS program

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Current Types of RAM(Covered more thoroughly in
next chapter)

• Dynamic RAM (DRAM)
• Common type of system memory
• Holds data for a very short time (3.6
  milliseconds)
• Requires refreshing by DMA chip
• parity, non-parity ECC (error
  checking/correction)
• Static RAM (SRAM)
• Doesn't need refreshing
• More expensive to produce, but much faster
• commonly used as cache memory
• L1 cache - in CPU chip
• L2 cache - in CPU housing

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Most Popular Types of RAM Modules
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ROM BIOS(aka firmware)

• The ROM BIOS chip on the system board contains
  programs for
• POST (startup BIOS)
• basic functions of the system (system BIOS)
• Some expansion cards carry own BIOS
• BIOS manufacturer
• Name displayed in boot process on top of chip
• notes
• Before XP, O/S relied on BIOS to do Plug-and-Play
  init
• XP doesn't use BIOS PnP data
• Older machines BIOS may only support 20GB drives
• You'll need to upgrade it
• EEPROM or flash ROM
• Electronically erasable programmable read-only
  memory
• Can update BIOS chip's programming see text