New Scheme for Tracking

1
New Scheme for Tracking

• Marvin Johnson

2
Equations

• Many advantages to equations
• give best possible rejection
• fast
• easy to check
• Significant disadvantages for 16 layers
• too many equations for cheap solution
• fiber inefficiencies require doing 15 out of 16
  etc.

3
equation generator

• formal mathematical formula
• computes the leading and trailing pt of a road
  through a given set of fibers
• equation is phi0phi - .3 r/pt
• phi0tangent of track at origin
• r and phi are the coords of the measured point
  (edge of fiber)
• pt is the momentum of the track.
• algorithm
• calculate phi0 for leading and trailing edge of a
  given set of fibers for a given pt
• select the max of the leading edge and min of the
  trailing edge (pos pt)
• if max lt min, we have a track
• more detail in D0 note.

4
new method

• instead of using equations, evaluate formula for
  each track
• convert parallel to serial
• Cant eval, formula for every pt
• can find common pt for large number of equations
• discard equations until there are only 2 pts for
  each inner and outer fiber
• keep about 95 of the efficiency
• example for pt gt 10 GeV/c
• 308 equations
• dropped 86, but kept 97.5 avg
• 286 equations
• dropped 75, 97.1 kept

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10 GeV/c ex.

• evaluate one layer per clock cycle - 16 cycles
• 122 MHz (16 cycles in 132 ns)
• about 10 common Pts per outer fiber (only 44
  done here)
• need 20 comparators
• calculate all possible equations
• At each layer for each comparator input the
  leading or trailing phi0 for fiber from memory if
  fiber present
• if no fiber present, keep old value
• compare with previous value and keep larger (or
  smaller)
• increment 4 bit counter if fiber present

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example cont.

• after 16 layers compare if min gt max
• if true, is counter above preset min.
• this is the number of fibers required - say 12
  out of 16.
• If OK, have a valid track.

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Comparison

• 222 equations _at_5 LUTs per eqn gives 1110 LUTs
  not counting routing
• Guess at new method is 110 for a factor of 10 in
  resources.
• limited by memory width
• VIRTEX II has 511 36 bit words.
• use only 32 words because of timing
• FPGA with wider memory would make a big
  difference
• Additional memory must come from distributed
  memory.

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Block Diagram
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Summary

• New algorithm gives the same results as equations
• Uses about 1/10 the resources (excluding memory)
• Includes inefficiencies with little added
  resources
• Requires 122 MHz operation
• Narrow memories are a problem
• Current solution does not do the gap between
  outer layer fibers
• Simple to add but requires wider memory and about
  16 comparators