The ARS frontend chip for ANTARES:

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• The ARS front-end chip for ANTARES
• Strengths and WeaknessesE. Delagnes1 with
  contributions of
• P.Coyle2,F. Druillole1,C. Donzaud3, A. Kouchner4,
  D. Lachartre5,S. Loucatos1,J.P. Pineau6, P.
  Payre4, J.P. Schuller1, B.Vallage1
• 1 CEA/DAPNIA SACLAY, 2 IN2P3/CPPM, 3 IPNO-Paris
  XI, 4 APC PARIS VII, 5 now with CEA/LETI
  (Grenoble), 6 IN2P3/IRES.
• EMAIL eric.delagnes_at_cea.fr.

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The ARS in the Local Control Module
3 ARS board

• DAQ Board
• FPGA 106 gates
• VxWorks
• 100 Mbit/s

Clock board (50 ns)
Compass, tiltmeter
Power supply
Ethernet 100 Mbit/s ? 1 Gbit/s, hydrophon..
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The ARS chip requirementss

• First Level Functionalities
• Discriminate signals coming from the PMT.
• Measure their time (0.5 ns rms precision).
• Measure their charge.
• Bufferize and Derandomize the event flow.
• Convert charge time in digital data.
• Format the events serialize them toward the DAQ
  board.
• Oscilloscope mode.
• 2nd Level Functionalities
• Rate Monitor rate alarm.
• Filter by L1 and L2 (historical reason).
• Test Led generator.
• All this for a reasonable power consumption and a
  low cost.

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The ARS Chip structure.
20MHz rate
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The ARS chip dead times and special mode of
operations

• Analog integrating storage in FIFO time
  300ns.
• SPE event readout time (Q time) 2µs.
• waveform readout time 180 µs.
• Dynode readout time 360 µs.

To minimize deadtime - two ARS are working
alternatively. - communication between them by a
token ring protocol.
Condition to pass the token from ARS1 to ARS2.

•  Special  mode of operations
• All SPE.
• Readout without L1 and L2
• All waveform.
• Triggering by slow-control.

Standard mode of operation !
For debugging and calibration
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Some ARS building blocks detection and Pulse
Shape discrimination
Goal reduce the waveform rate to 1 of events
(experimentally verified on MILOM)
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Some ARS building blocks Time Stamp and
integrator
Time stamp 24 bit counter (50MHz) analog
interpolator
 100 efficient gated integrator  Based on 3
capacitors cycling structure. Gate duration
cycling clock programmable
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Some ARS building blocks The mixed-mode FIFO and
the ADC
16 cells deep Mixed mode asynchronous FIFO It
seems crasy but It works !!!
The Successive approximation ADC LSB and
Baseline values can be  dynamically  changed
depending on the measurement Deliver 8 bits,
but only 6 bit resolution (due to NLD).
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Some ARS building blocks The Analog Ring Sampler.
ARS0
Continuously samples the analog signal in a
circular switched capacitor array. Stopped
after a programmable delay when a Trigger
occurs. Read back sequentially at a lower
frequency. 4channels anode, clk dynode1
dynode 2 128 cells deep.
Very High sampling Frequency of 640MHz Possible
thanks  sampling DLL  structure. Sampling
clock servo controlled on chip gt low jitter and
drift.
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The ARS chip some characteristics

• Many parameters programmable by slow control
  (scan-path).
• Original ARS Philosophy
• No special work has been done to limit the
  chip-to-chip spread of analog blocks
  (discriminator, integrator,TVC, ADC).
• As we are in the digital era, these spreads can
  be digitally reduced by correct tuning of
  adequate slow-control parameters.
• gt Practically unfeasible at large scale, work
  made only for the discrimination threshold.
• For the other parameters, common settings are
  used.
• Use of a custom current mode digital (DCL)
  standard to communicate with the outside world gt
  need of the ARS conv chip. Less noisy than CMOS
  levels.
• 80 of the digital part is asynchronous.
• 100 of the design is full custom.
• The chip fill factor is 95

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The ARS chip layout
AMS CMOS0.8µm technology. 70000 transistors. 23
mm2 Packaged in QFP100 package
Produced in 2004 on one of the last batch of the
technology.
Needs 5 protoyping before production
The ARS chip a mixed-mode analog digital system
on chip
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The ARS chip main performances

• Not the  typical  best performances but the
  real values measured or used for acceptance on
  the test bench during production

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ARS chip production test

• Very complete test, functional parametric.
• 15 min long.
• Acceptance windows based on specifications but
  also on statistics.
• Check the spreads and fill database.
• End of serie-test in sept 2005 all the chips are
  now delivered.

2 of the 30 distributions of parameters studied
Wide spread of L0 discriminator threshold (40mV
pp2/3 SPE) need for a threshold/chip
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The ARS chip production

• Over 5000 chips tested
• Yield 51 not so bad for a so complex chip.
• Only 9 of the chips are not functional at all.
• Chip to chip spread is the same as in
  pre-production.

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The ARS on the ARS MB

• Performances of ARS_MB on test bench are very
  similar to those of ARS
• (As expected) still works up to more than 1 MHz
  random rates.
• But some offsets and transfer functions are
  slightly different.
• Again different when integrated in the LCM.
• Calibration must be done at the last moment.

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The ARS in operation random time distribution,
Differential Non-linearity.

• TVC Differential Non-linearity due to ADC (due to
  settling times in successive approximations).
• If re-binned by 4 flat distribution
• gt compatible with 6 bit resolution (initial
  specification).
• Not a problem for TVC, waveform.
• Not a problem for integrator in standard
  operation
• gt But integrator difficult to use to set the
  threshold

SPE histo with integrator
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The ARS in the deep sea some results with the
MILOM
SPE spectra with different thresholds (integrated
waveform)
One event clock waveform
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2
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Good correlation Waveform/Integrator
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The ARS in the deep sea some results with the
MILOM
Distribution of time difference between OM and
reference PM for LED Beacon pulses.
Includes electronics contribution but not time
walk neither PM TTS contributions. Within
expectation. (On lab measurements on LCM with
pulser gave 300ps rms)
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The ARS1 Time walk correction (dark room 2003).
Time Walk measurement
Time Resolution with laser Nphot1
Without walk correction ?tts 1.5 ns With walk
correction ?tts 1.3 ns
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The ARS dead time in the dark room (2003
measurements)
Delta T between consecutive hits of Single OM
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If we had to redesign the ARS some thoughts
about the design architecture

• Too complicated design
• 5 functions timing, integrator,waveform anode
  and dynode, and FIFO could be probably done by an
  unique block (a single high dynamic range SCA
  with two modes of read-out).
• The Token ring adds some complexity all should
  be done in one chip. The threshold must me
  equilibrated to equalize the rate
• Too many  parasitic  functions (counting rate
  monitor) gt could be done elsewhere with a
  dedicated data flow.
• Interest of data formatting and full readout
  control inside the chip ? gt In my opinion, the
  ARS is too clever it should be a pure slave
  driven by an external controller.
• Should the ADC be integrated in the chip ?
• The more the chip is complex, the more the test
  (and qualification) is hard.
• Too many pins connected to the input signal (pb
  for impedance matching).
• Too many external components External references
  ARSconv external data synchronizer could be
  avoided (by a better chip design).

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If we had to redesign the ARS some thoughts
about the design methodology.

• Concerning digital design
• The massive use of asynchronous logic is a
  nightmare cause of 90 of the problems we had on
  the 4 last prototypes. With our design tools
  proof of working by simulation is impossible.
• Too many different clocks (reference, sampling
  reference, readout, slow-control).
• For such a complex design need for a high level
  language description.
• DCL logic levels (good idea, but too sensitive)
  should be replaced by LVDS standard for high
  speed communication.
• Concerning analog design
• The original philosophy compensate the analog
  spreads by digital tuning is difficult to apply
  for large scale experiment should be automatic
  (dangerous) or very limited to second order
  tuning.
• A real design work has to be done on the spread
  (careful design of blocks and references,
  differential designs) checked by Monte-Carlo
  simulations.

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If we had to redesign the ARS some reflexions
about the design methodology.

• Avoid so compact designs
• For non critical blocks, some space margins
  should be taken to allow future modification/
  evolution (was impossible in this case).
• Such a complex chip shouldnt be a single person
  work but should be designed by a team
• - to allow open discussions on specifications,
  architecture and design.
• - to filter the  too-good  or
   too-innovative  ideas.
• - it is safer in one of the designer leave is
  lab (time scale of our projects).

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The ARS1 conclusion

• The ARS1 front-end chip is working satisfactorily
  in real conditions.
• Only one part of its functionalities is used in
  ANTARES.
• All the needed chips for ANTARES have been tested
  and delivered.
• But this chip is very (too?) complex and a real
  expertise is needed to use it properly.
• For the future experiments, we should absolutely
  avoid this.
• Saclay is interested to work on the next
  generation
• We are starting to think about a new architecture
  based on what we have learnt on ARS1.
• We are open to discussions and collaborations.

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