OUTLINE

1
Lecture 42
Note HW14 was updated this morning. (There are
only 4 problems!)

• OUTLINE
• IC technology
• MOSFET fabrication process
• CMOS latch-up
• Reading Chapter 4

2
Integrated Circuit Technology
Planar fabrication process Simultaneous
fabrication of many chips on a wafer, each
comprising an integrated circuit (e.g. a
microprocessor or memory chip) containing
millions or billions of transistors
Method Sequentially lay down and pattern thin
films of semiconductors, metals and insulators.

• Materials used in a basic CMOS integrated
  circuit
• Si substrate selectively doped in various
  regions
• SiO2 insulator
• Polycrystalline silicon used for the gate
  electrodes
• Metal contacts and wiring

3
Formation of Insulating Films

• The favored insulator is pure silicon dioxide
  (SiO2).
• A SiO2 film can be formed by one of two methods
• Oxidation of Si at high temperature in O2 or
  steam ambient
• Deposition of a silicon dioxide film

Applied Materials low-pressure chemical-vapor
deposition (CVD) chamber
ASM A412 batch oxidation furnace
4
Patterning the Layers
Planar processing consists of a sequence of
additive and subtractive steps with lateral
patterning

• Lithography refers to the process of transferring
  a pattern
• to the surface of the wafer
• Equipment, materials, and processes needed
• A mask (for each layer to be patterned) with the
  desired pattern
• A light-sensitive material (called photoresist)
  covering the wafer so as to receive the pattern
• A light source and method of projecting the image
  of the mask onto the photoresist (printer or
  projection stepper or projection scanner)
• A method of developing the photoresist, that is
  selectively removing it from the regions where it
  was exposed

5
Pattern Transfer by Etching
In order to transfer the photoresist pattern to
an underlying film, we need a subtractive
process that removes the film, ideally with
minimal change in the pattern and with minimal
removal of the underlying material(s)

• Selective etch processes (using plasma or
  aqueous chemistry)
• have been developed for most IC materials

Jargon for this entire sequence of process steps
pattern using XX mask
6
The Photo-Lithographic Process
optical
mask
Oxidation or thin-film deposition
photoresist exposure
photoresist coating
photoresist
removal (ashing)
photoresist develop
etch
optional additional process step(s)
spin, rinse, dry
7
Adding Dopants into Si
Suppose we have a wafer of Si which is p-type and
we want to change the surface to n-type. The way
in which this is done is by ion implantation.
Dopant ions are shot out of an ion gun called
an ion implanter, into the surface of the wafer.
Eaton HE3 High-Energy Implanter, showing the
ion beam hitting the end-station
Typical implant energies are in the range 1-200
keV. After the ion implantation, the wafers are
heated to a high temperature (gt1000oC). This
annealing step heals the damage and causes the
implanted dopant atoms to move into
substitutional lattice sites.
8
N-channel MOSFET
4 lithography steps are required 1. active
area 2. gate electrode 3. contacts 4. metal
interconnects
channel width, W
gate length, Lg
9
CMOS Technology

• Both n-channel and p-channel MOSFETs are
• fabricated on the same chip (VTp -VTn )
• Primary advantage
• Lower average power dissipation
• Ideally, in steady state either the NMOS or PMOS
  device is off, so there is no DC current path
  between VDD GND
• Disadvantages
• More complex (expensive) process
• Latch-up problem

10
Need p-regions (for NMOS) and n-regions (for
PMOS) on the wafer surface, e.g.
ND n-well
NA

• Single-well technology
• n-well must be deep enough
• to avoid vertical punch-through

p-substrate
ND n-well
NA p-well

• Twin-well technology
• Wells must be deep enough
• to avoid vertical punch-through

p- or n-substrate (lightly doped)
11
Modern CMOS Fabrication Process

• A series of lithography, etch, and fill steps are
  used to create silicon mesas isolated by
  silicon-dioxide
• Lithography and implant steps are used to form
  the NMOS and PMOS wells and to set the channel
  doping levels

12

• The thin gate dielectric layer is formed
• Poly-Si is deposited and patterned to form gate
  electrodes
• Lithography and implantation are used to form
  NLDD and PLDD regions

13

• A series of steps is used to form the deep source
  / drain regions as well as body contacts
• A series of steps is used to encapsulate the
  devices and form metal interconnections between
  them.

14
Intels 65 nm CMOS Technology
NMOSFET

• Lg 35 nm
• Tox 1.2 nm
• Strained Si channel
• NMOS tensile capping layer
• PMOS epitaxial Si1-xGex embedded in S/D

PMOSFET
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CMOS Inverter
Vin
VSS
VDD
Vout
n
p
p
n
n
p
SiO2
n-well
p-Si
VDD
Equivalent circuit
Vin
Vout
16
CMOS Latchup
Coupled parasitic npn and pnp bipolar transistors
If either BJT enters the active mode, the SCR
will enter into the forward conducting mode
(large current flowing between VDD and GND) if
bnpnbpnp gt 1 gt circuit burnout!

• Latch-up is triggered by a transient increase in
  current, caused by
• transient currents (ionizing radiation, impact
  ionization, etc.)
• voltage transients
• e.g. negative voltage spikes which forward-bias
  the pn junction momentarily

17
How to Prevent CMOS Latchup
1. Reduce minority-carrier lifetimes in
well/substrate 2. Use highly doped substrate or
wells
n-well
(a)
Rsub npn
p epitaxial layer
p-substrate
Rwell pnp
n
(b)
p-sub
n
retrograde well
18
IC Technology Trends

• Increasing of levels of wiring (Cu
  interconnects)
• Up to 8 levels of metal are used in ICs today.

Photo from IBM Microelectronics
Gallery Colorized scanning-electron micrograph
of the copper interconnect layers, after removal
of the insulating layers by a chemical etch

• Increasing variety of materials
• high-k gate dielectric, metal gate, low-k
  intermetal dielectrics, etc.

• Continued scaling of MOSFETs toward 10 nm Lg
• CMOSFETs with gate lengths below 20 nm have
  already been demonstrated by leading
  semiconductor manufacturers.
• ? The most advanced transistor designs are based
  on UC-Berkeley research (Profs Hu, King Liu,
  Bokor).