Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties

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Automatic Discovery of RTL Benchmark Circuits
with Predefined Testability Properties
Tomá Pecenka, Zdenek Kotásek, Luká Sekanina,
Josef Strnadel Faculty of Information
Technology Brno University of Technology Brno,
Czech Republic EH 2005, Washington D.C.
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Motivation

• Increasing complexity of electronic circuits
  (Moores law) implies the need for sophisticated
  CAD tools
• We have to evaluate the quality of CAD tools
• A group dealing with the diagnostics and
  testability of ASICs works at FIT in Brno
• The group
• develops CAD tools for diagnostics and
  testability analysis of digital circuits
• evaluates the CAD tools using benchmark circuits

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Benchmark sets

• Existing Benchmark Sets
• ISCAS85 / 89 gate level
• ITC99 (revision 00) gate level RT level
• ITC02 SoC benchmarks - block level
• Complexity of benchmark circuits vs. technology
  potential
• Benchmark circuits gate level
• the most complex circuit ITC99 (b15_1)
  13098 gates and 449 registers
• more complex benchmark circuits (e.g. b16, b17,
  ...) combine some of smaller circuits
• Current digital circuits
• FPGA Xilinx Virtex 4 - 178000 slices (LUT /
  register / ...)
• IO Intel Itanium II - 220000000 transistors
• Benchmark circuits with the required complexity
  are missing

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Synthetic benchmark circuits exists

• Generation of circuits with predefined properties
• M. Hutton place route algorithms in FPGA
• K. Iwama logic optimizers
• J. Pistorius, D. Stroobandt partitioning
  algorithm
• ...
• Can EA produce synthetic benchmark circuits with
  predefined diagnostic properties?

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Objectives

• To develop a system which is able to
  automatically generate large benchmark circuits
  with predefined diagnostic properties.
• Note Testability of a circuit can be estimated
  in O(n2) gt fitness evaluation would be very fast
  even for large circuits!

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Testability analysis (espec. for ASICs)

• informs us how difficult is to test a circuit
• is based on the controllability observability
  analysis
• Controllability is the ability to set values of
  inputs of any component from the primary inputs
  of the circuit
• Observability is the ability to observe values of
  outputs of any component at the primary outputs
  of the circuit
• If inputs are controllable and outputs are
  observable then we can test any component of the
  circuit using primary inputs and outputs (i.e. we
  can access any component of the circuit)

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The concept of controllability (1)

• Controllability how difficult is to set a value
  for a component input
• Example the controllability of node (1) 1.00
  (100, maximal) because a direct wire exits from
  primary input i3

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The concept of controllability (2)

• Controllability how difficult is to set a value
  for a component input
• Example the controllability of node (2) 0.90
  (90) because a path exist from i1 via ADD1 and
  REG1.

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The concept of controllability (3)

• Controllability how difficult is to set a value
  for a component input
• Example the controllability of node (3) 0.00
  (0) because no path exists from primary inputs
  via LOGIC

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Testability of the circuit

• Observability
• is defined in the same way as controllability
• Controllability of the circuit
• is the average controllability of all component
  inputs
• Observability of the circuit
• is the average observability of all component
  outputs
• Testability controllability observability

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Relation of testability and the number of test
vectors

• High testability
• low number of test vectors
• high fault coverage
• Low testability
• high number of test vectors
• low fault coverage
• The relation is important for a commercial
  production of ASICs
• the number of test vectors has to be minimized

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Design method

• Input (provided by user)
• the number and type of components
• e.g. 5xSUB(8) , 5xADD(8), 5xMUX2(8), 5xADD(16),
  5xSUB(16), 5xMUX2(16).
• the number of circuit primary inputs and outputs
• e.g. 5 x 8bit input, 5 x 8bit output
• testability properties
• average controllability (e.g. 70)
• average observability (e.g. 80)
• Output
• synthesizable benchmark circuit in VHDL
• Evolutionary design method - EP
• Fixed-length integer chromosome
• Mutation only (2)
• Elitism
• Generations 50-200
• Population size 20-50

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Circuit representation and mutation
Mutation type 1
Mutation type 2
Representation
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Options for fitness function

• Option 1
• to use a commercial test vector generator
• low number of test vectors and higher fault
  coverage gt higher fitness
• time consuming!
• Option 2
• to estimate the testability using a method
  described in Strnadel, J. Testability Analysis
  and Improvements of Register-Transfer Level
  Digital Circuits, PhD thesis, Brno University of
  Technology, 2004

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Fitness function

• Evaluation of circuit structure and interconnects
• Testability evaluation
• Fitness

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Results (controllability 33)
Population 25, generations 50, runs 5,
mutation 2, replacement100 (elitism).Number
of components 30, number of primary
inputs/outputs 5.
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Results (observability 33)
Population 25, generations 50, runs 5,
mutation 2, replacement100 (elitism).Number
of components 30, number of primary
inputs/outputs 5.
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Example of an evolved circuit
Testability properties Required
Measured
Controllability
33 36,7
Observability
20 20,4
Components 5xSUB(8) , 5xADD(8), 5xMUX2(8),
5xADD(16), 5xSUB(16), 5xMUX2(16). Population 25,
generations 50, mutation 2, replacement100
(elitism).Number of components 30, number of
primary inputs/outputs 5/5.
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Examples of results
Intel Xeon 2.8GHz, 1GB RAM
Required controllability/observability
33. Population 25, generations 200, runs 5,
mutation 5, replacement 95 (elitism).
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Conclusions

• SW for automatic design of benchmark circuits
  with predefined diagnostic properties was
  developed.
• The program is able to produce relatively large
  circuits.
• Diagnostic properties of the circuits produced
  are satisfactory in some range.
• Future research
• The quality of the evolved circuits will be
  verified using a commercial ATPG.
• Testability analysis will be improved.