A 60GHz Antenna Array FrontEnd in CMOS

1
A 60GHz Antenna Array Front-End in CMOS

• BWRC Research Retreat
• Sayf H. Alalusi
• Summer 2003

2
CMOS for 60GHz
fT (speed)
100 G
0.13u
0.18u
30 G
0.25u
0.35u
0.5u
10 G
0.6u
L min
0.8u
1u
3 G
1.5u
1 G
2u
(Hz)
3u
75
77
79
81
83
85
87
89
91
93
95
97
99
01
03
Year

• Getting any gain out of CMOS circuits will be
  difficult.
• fT gt 60GHz, not fT gtgt 60 GHz
• It may not be a matter of trade-offs anymore,
  performance of a lone circuit may be inadequate.

3
Adaptive Beamforming for High Gain

• Antenna needs high gain (12-15dB) in an arbitrary
  direction
• Gain ltgt Directivity ltgt Beamwidth-1

N number of antennas
Beam pattern controlled by antenna weights.

a0
a1
a2
aN-1
x(t)

• Adaptive Beamformer
• Can adapt to achieve high gain in any direction,
  regardless of physical orientation
• Added bonus attenuate interfering signals from
  other directions
• Requires digital control and computation for
  adaptation of weights.

4
Adaptive Beamforming Advantage 1 Directivity in
Any Direction

• Direct all energy along chosen path only.
• Preferentially receive energy from chosen path
  only.
• High gain in any direction, controlled
  electronically.

Can change nearly all channel parameters.
5
Adaptive Beamforming Advantage 2 Subdivision
Limited performance at 60 GHz
Relaxed spec.s for individual components

• Use Circuit level parallelism to achieve our
  performance goals.
• Use N power amplifiers to get total transmit
  power
• Use N low noise amplifiers to receive N copies of
  the signal
• This is critical because of limited performance
  of CMOS circuits
• due to low voltage swing, operation close to fT,
  etc.

6
Digitally Weighted Architecture

• Optimal capacity for all channel conditions N
  data streams
• Very high hardware complexity N full
  transceivers
• Very high system power consumption

Overlay of N Independent Beams
s1(t)
r1(t)
r2(t)
s2(t)
r3(t)
s3(t)
7
RF Phase Shifter Architecture

• 1 data stream, RF phase shifters only, digitally
  controlled
• Achieves high antenna gain in an arbitrary
  direction
• Low hardware complexity N RF phase shifters
• Low system power consumption phase shifters only
  switch at Doppler rate.

r(t)
s(t)
a0
a0
a1
a1
S
a2
a2
8
Antenna Elements

• Antenna needs to be ?/2 long ?/2 2.5mm in
  free space
• Need ?/2 lateral spacing between element origins
• Antenna unit cell is approx. 2.5mm x 2.5mm (?/2 x
  ?/2)
• Typ. laptop is 200mm x 300mm 80 x 120 antennas
  -- N 9600!
• Typ. PDA is 70mm x 110mm 28 x 44 antennas -- N
  1200!
• Typ. PC Card antenna is 20mm x 50mm 8 x 20
  antennas -- N 160!
• Only need N16 (12dB), so this should not be a
  problem physically.

10 mm
2.5mm
2.5mm
Dipole or Patch
2.5mm
Unit cell can be tiled to form array.
9
RF Phase Shifters

• Provides weighting of array coefficients at full
  RF.
• 3 major types
• Passive Tuned high-, low-, all-pass filter ok,
  but require tunable elements on-chip, also have
  limited tuning range.
• Switched Delay Lines Provides phase shift
  through actual time delays. Virtually guaranteed
  to work, but bulky in CMOS.
• Vector Modulator Just need variable attenuators
  on the I and Q signals (gives us full phase and
  magnitude control).

Vector Modulator
?
x(t) e(j?t ß)
x(t)
90
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Phase Shifter Accuracy

• Primary problem is directivity care about gain
  and direction of main beam.
• For N 16, quantizing to 3 levels ( 1, 0, -1)
  on each of I and Q channels preserves main beam
  direction and angle.

2º
Angle error
-8º
3
Directivity error
2
1
11
IQ Generation at Receiver

• Must generate IQ before mixer, at full carrier
  freq.
• This is needed for the vector modulator
• There are 2 common ways of doing this
• Microwave, e.g. 90 degree Hybrid (a.k.a. 3-dB
  Hybrid)
• Lumped, e.g. 45/-45, using high-pass and
  low-pass filter sections

Microwave
Lumped
in
I
in
I
isolated
Q
Q
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Summary

• 2 ways that an adaptive array increases EIRP in
  any direction
• Antenna gain
• Combining performance of arrays of traditional RF
  circuit blocks
• Array of 16 antennas and very simple RF phase
  shifters will give the needed performance for a
  1Gbps wireless link at 60GHz in CMOS.
• Future Work
• Evaluate specific architecture and circuit
  tradeoffs
• Testing environment, where partition, Packaging
  technology
• Antenna selection and design
• Digital control and adaptation algorithms

13
Detailed Link Budget Calcs

• a extra EIRP needed antenna gain and/or xmit.
  power
• Shift 802.11a to 60GHz, 1Gbps Pt14dBm, NF5dB,
  64 QAM
• These optimistic numbers give a 39 dB !
• More realistic Pt10dBm, NF10dB, BPSK a 26
  dB

e.g., for 802.11a, at 10m need a -6dB!
14
Baseband Analog Architecture

• 1 data stream, antenna weights applied at
  baseband
• Achieves high antenna gain in an arbitrary
  direction
• Intermediate hardware complexity N RF mixers
• Intermediate power consumption

s(t)
a0
a0
r(t)
a1
a1
a2
a2
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Antenna Array Patterns

• ET F(?,I0) (a0a1ejkdcos?a2ej2kdcos? )
  EFAF
• Element Factor (EF) is the field of a lone
  element.
• Only Array Factor (AF) can be controlled
  electronically, by changing the magnitude and
  phase of ai.
• For a beam to look at direction ?,
• set progressive phase
• ?ai1 - ?ai -kd cos(?)
• ai 1

k2p/?
r1
r2
T2
T1
kd cosT Phase shift due to physical separation.
d
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Element Factors

• Common array elements Dipole, Patch
• Other arrays 2-dim. or even 3-dim. arrays
• Element is chosen to be isotropic over region
  of interest
• Element can be chosen for its properties in other
  dimensions

Parallel
AF
Collinear
AF
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Examples 16-Antenna Array

• Uniform Array mag. 1, progressive phase ß,
  uniform spacing
• We only need phase shifters!

N 16 kd p
Broadside ß 0
Isotropic radiators
D12 dB
Phased ß-kd cos(60)
D12 dB
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Number of Antennas

• Directivity D0Umax/U0 AFmax2 N
• Half Power Beamwidth(HPBW) 2arccos(1-?/Nd)
• Nulling of interferers reduces main beam gain (a
  little).
• Physical size of antenna array is not an issue
• Circuit complexity grows as N

D0
HPBW
(Uniform Array)
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Array of Power Amplifiers

• At 60GHz, we are power limited, so let max. PA
  power Pt
• One factor of N in EIRP from directivity of array
  pattern
• Another factor of N in EIRP from combining power
  of N PAs
• As we add antennas total gain is Pt N2
• 6dB EIRP for each doubling of N, with constant
  individual PA power
• 24 dB EIRP for N 16 antennas, compared to base
  system.

Original PA
Constant Individual Transmit Power
20
Array of Low Noise Amplifiers

• Each added antenna receives another copy of the
  signal for free that is perfectly correlated, so
• (S1 S2)2 S12 2S1S2 S22 4S2 gt
  N2S2
• And another noise source, totally uncorrelated,
  so
• (n1 n2)2 n12 2n1n2 n22 2n2 gt
  NE2n
• NF (NF of lone LNA)/N
• Since CMOS is performance limited here also
• Also effective voltage gain of N(gain of one LNA)

a0
a1
21
/- Vector Modulator

• Only need to select ,- or 0 for I and Q.
• Then add the 2 signals to get the desired phase
  shift.
• Very easy if use differential signaling, but not
  necessary.

SEL
SEL-

Vin (I or Q)
-

VO
-
SEL0
SEL0
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Target Prototype
One CMOS Chip, 0.13um
Each block PA, LNA, Phase Shifters
Each block 3 b. for phase 1 b for TX/RX
I
60 GHz
Q
n

• Antennas need to be off-chip, in the package.
  (LTCC? PCB?)
• Path length is not critical array is adaptive
  and weights are relative.