Student

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Hardware Accelerator for Ray Tracing
Student Parikshit Patidar Supervisor Prof
Anshul Kumar Dr Prem Kalra PhD Involved Anup
Gangwar
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Contents

• Introduction
• Objective and Motivation
• Scope
• Ray tracing and RayLab
• Hardware Accelerator and its performance
  estimation
• Memory wrapper
• Accelerator
• Work done
• Work to be done

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Introduction

• Ray-tracing is a rendering technique that
  calculates an image of a scene by simulating the
  way rays of light travel in the real world.
• Hardware accelerator for ray tracing is a
  dedicated device that improves the speed of
  calculation of final image by performing the
  computation intensive tasks in parallel and
  provides an interface to program that can use it.

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Objective

• The objective of the project is to design a
  hardware that accelerates the speed of
  computation of final image by embedding all the
  computation intensive routines and provides a
  interface to it.

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Accelerator
Host CPU
PCI Interface
Memory
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Design
Raylab Ray tracer
Interface (Software interface Wrapper)
Accelerator
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Motivation

• Ray Tracing is the most powerful photo realistic
  image generation technique
• Simple and easy to implement in hardware
• Can be easily extended to add additional effects
  like shadow, texture map
• Ray tracing is amenable to massive parallelism
  given the proper architecture.

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Scope

• The project mainly deals with the optimization of
  the available
• Ray Tracer i.e. RayLab. RayLab is a ray tracer
  that has following
• capabilities
• Primitive Objects Sphere, Cone, Cylinder,
  Parallelopiped, Torus, Parallelogram, Triangle,
  Ellipsiod etc
• Constructive Solid Geometry With the help of
  basic objects it creates other arbitraty shapes.
• Light Source Area and Point light source.
• Advanced Effects Soft shadow, Antialiasing,
  Reflection, Refrection, Transparency, Glossy
  effect etc.

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Scope (contd.)

• The ADM-XRC supports high performance PCI
  operation
• It has the following features
• Two high speed DMA controllers that can achieve
  rates of 120Mbytes/sec.
• Physically conformant to IEEE P1386 Common
  Mezzanine Card standard
• User clock programmable between 0.5MHz and 100MHz
  
• Local bus speeds of up to 40MHz

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Ray Tracing

• Ray Tracing is a rendering method that generates
  an image of
• given mathematical scene. The light ray is shot
  for each pixel on
• the view plane (monitor screen) towards the
  object in the scene.
• The pixels color is set to that objects color
  which has closest
• point of intersection.

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Light Source
Scene
Intersection points
View Plane or Screen
Viewers eye
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RayLab

• Features
• Primitives sphere, cone, cylinder, plane,
  ellipsoid, box, disc etc.
• Texture mapping
• Transformations scaling, rotation and
  displacement
• Constructive solid geometry
• Advanced Effects Soft shadow, Anti-aliasing,
  Reflection, Refraction, Transparency, Glossy
  effect etc.

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Computation intensive functions
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Problems with RayLab

• Doing one task at a time (dataflow)
• Lots of parameter passing in selected routines
• It is not designed to be ported onto hardware

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Modifications

• Threads are inserted so that multiple rays can be
  calculated in parallel.
• All the objects are collected initially and sent
  to local memory of hardware when it is
  initialized.
• Sending multiple sets of data, so that hardware
  is called less number of times.

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Hardware Accelerator

• Hardware accelerator is a dedicated device that
  encompasses all the time consuming routines.
• It is an FPGA board with PCI Interface
• It can do multiple tasks in parallel by having
  multiple execution units running independently
• It has its own local memory to store the inputs
  and generated results

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Memory Wrapper

• It is developed for ADM-XRC card
• Provides interface between host machines data
  bus and FPGAs local memory
• Support both programmed I/O and DMA transfer
• Provides interface between execution unit on FPGA
  and its local memory.
• It supports four memory banks for simultaneous
  use
• Support two different modes user mode wrapper
  mode

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Performance Estimation

• Host Pentium 4
• Hardware accelerator FPGA board with 4 execution
  units, 100MHz clock
• speed, 120Mbps (120/8MBps) transfer speed.
• Input scene 27 objects
• Time taken by selected routines on host machine
  2945 seconds
• Initial data transfer time (20027)/(120/8)
  10-6 360 10-6 seconds
• Input generated result transfer time
  28/(120/8)10-6 36/(120/8)10-6 4.27
  10-6seconds
• Total number of cycles needed by each computation
  units 300 (27 / 4)
• Hardware is called 26893845.
• Total time needed on hardware accelerator (360
  26893845(1.87 2.4 20.25)) 10-6
• 659.44 seconds
• Gain (2945-659.44)/2945 77.61

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Accelerator

• It incorporates all the computation intensive
  routines of the ray tracer
• There are multiple copies of execution module,
  which are capable of running simultaneously and
  independently
• Each module has its own memory bank
• Each module can run different set of routines and
  can operate on different set of data
• It has two main components controller and
  sub-module

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Accelerator
BoundCheck
TransfornLine
VectorOperation
IntersectSphere
PostTransform
Controller
Memory
Registers
FPU 1
FPU 2
FPU 3
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Controller

• Initialize the memory to be used by modules
• Generate control signals for various modules
• Maintain mutual exclusion for FPUs and memory
• Generate final results in local memory

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Sub-modules

• Each sub-module corresponds to a routine in the
  ray tracer
• Take the input from the specified location in
  local memory
• Perform computation on the input data
• Generate output at specified location
• Return control to controller

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Work done in last semester

• RayLab is modified so that multiple tasks can be
  generated and it can use hardware efficiently
• Accelerator is designed and all the internal
  modules are identified
• The internal modules identified are
• Bound check
• Generation of transformed ray
• Processing of intermediate data
• Generation of final results
• Written a sub-module for the routine BoundCheck

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Current Status

• One more module VectorOperation is added to the
  design
• Written code for VectorOperation and
  IntersectSphere
• Changed the way of communication between
  controller and submodules
• Three floating point units have been added to the
  Accelerator
• Integrating BoundCheck, IntersectSphere,
  Controller, Registers and memory.

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Work to be done

• Implementation of TransformLine PostTransform
  submodules
• Make this overall system run error free
• Synthesize the Accelerator
• Minimize the number of clock cycles needed for
  overall task
• Minimize the number of calls made to hardware,
  i.e. perform more work in one call
• Minimize the data transfer between hardware and
  software

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• Thanks