Gentest: An Automatic TestGeneration System for Sequential Circuits

1
Gentest An Automatic Test-Generation System for
Sequential Circuits

• Mohamed Abougabal,
• Wael Hermas,
• Tarek Saad,
• Rami Abielmona
• ELG 5194
• Wednesday November 22, 2000
• Prof. Sunil Das

2
Presentor Mohamed Abougabal

• Introduction Gentest
• Definition
• Converting Sequential to Combinational circuit
• Gentest Architecture

3
Introduction to Gentest

• Definition
• Gentest is an automatic Test-Generation System
  for sequential Circuits.
• Gentest 
• Was introduced because of the rapid growth of
  VLSI chips, we certainly know that these chips
  contains faults. Therefore we need Gentest to
  help us achieve the high fault coverage. 
• It Overcomes the inefficiency of previous ATG
  methods for sequential circuits by combining a
  sequential test generator with a concurrent
  fault simulator.

4
Test Generation Techniques (1)

• 1. Manually write test vectors (write a sequence
  of values provided to the circuit input)
• Disadvantage
• Its tedious and time-consuming process  
• 2. BIST Built-In-Self test Circuit The circuit
  itself create test vectors . The circuit
  generates random patterns that can thoroughly
  test a combinational circuit.
• Disadvantage
• It requires more circuitry.
• The cost of chip is higher because of the area.
• It causes the chip to be slower
• Finding the exact fault coverage for test vector
  is difficult. 

5
Test Generation Techniques (2)

• 3. ATG Automatic Test Generation.
• Given the description of a circuit , ATG programs
  deliver a set of vectors.A complete ATG
  algorithm guarantee finding a test for a fault if
  one exists.
• Disadvantage
• Its not practical for every circuitSince most
  of the sequential circuits are practical circuits
  we can use Scan Design Techniques to convert
  sequential circuits into combinational circuits.
• The difficulty of sequential test generation lies
  on the large number of decision steps.

6
Converting Sequential to Combinational Circuits
(1)

• The First Sequential Test Generation Algorithm
  were just an extension of the combinational test
  algorithm.
• Those Algorithm are
• D- Algorithm
• Podem (Path-Oriented Decision making.)
• We can model Sequential circuits by two blocks
  (Combinational and Memory) 

7
Converting Sequential to Combinational Circuits
(2)
Figure 1. Sequential circuit model
8
Iterative Logic Array Method (1)

• Now use this same concept and expanding on it we
  can model a Sequential circuits into
  Combinational in time Domain and this method is
  known as The Iterative Logic Array Method.
• In Figure 2 Each copy corresponds to the
  circuit behavior at one time frame. Therefore
  D-Algorithm and Podem can be applied because
  these are combinational circuits.

9
Iterative Logic Array Method (2)
Figure 2. Iterative logic array model
10
Iterative Logic Array Method (3)

• Problems
• Inefficient in dealing with repeated faults
  sites.
• Excessive memory usage because the circuit must
  be saved for each time frame in test sequence.
• Solution
• Mallela and Wu have introduced STG2 (sequential
  test generator using the Back algorithm)
• Then Gentest was introduced. Gentest is
  combination of STG2 and Csim ( Concurrent fault
  simulator).

11
Gentest Architecture (1)

• Functionality of
• STG2 Generates a test sequence for every target
  fault selected by Gentest
• Csim Determines which faults are detected by
  the STG2-generated test sequences.
• Gentest Submits the vectors created for fault
  detection to a fault simulator.
• Now the overall operation of Gentest .
• 1. The user can provide a fault list otherwise,
  Gentest creates one after collapsing all
  equivalent faults.
• 2. User can set a time limit or let it be
  generated by an experimental formula in SGT2.
• 3. User can provide some initializing vectors
  that Csim will simulate to initialize the circuit

12
Gentest Architecture (2)

• 4. Gentest selects an untried and undetermined
  fault as a target fault for SGT2.
• 5. SGT2 tries to generate a test sequence for the
  target fault.
• 6. So by looking at steps 1 to 5. Test sequence
  can be generated in one of the three cases
• Test sequence can be generated to detect the
  target fault
• The target fault can prove untestable
• Time limit can be reached.
• In either of these cases Gentest returns to step
  4.

13
Presentor Wael Hermas

• Iterative Logic Array Model
• Podem Algorithm
• Putzolu and Roth Test Method
• STG2 Discussion
• Back Algorithm

14
The Test Generator

• Problems of previous test generation method
• Iterative Logic Array Model
• Podem Algorithm
• Putzolu and Roth Test Method

15
Iterative Logic Array Model (1)

• The following figure (refer to figure 3) shows a
  sequential circuit with a single stuck-at fault.
• Each is the fault site in each time frame.
• Using the iterative logic array model, this fault
  has a repeated fault effect at every time frame.

16
Iterative Logic Array Model (2)
Figure 3. General model of a test sequence
17
Podem Algorithm

• Assume that the fault, in the previous example,
  can only be tested by a test sequence with eight
  test vectors
• Lets us say that the Podem algorithm needs to
  know that the propagation of fault effects should
  start after time frame 5 (Podem algorithm will
  stop at frame 4) since all the sensitized paths
  are blocked
• Without knowing the test sequence, having this
  information would be impossible, therefore we can
  conclude that Podem algorithm can be very
  inefficient in generating test sequence for
  sequential circuits.

18
Putzolu and Roth Test Method (1)

• Uses the two-step approach of the D-algorithm to
  generate the test sequence.
• Their method has the same problem as Podem at
  time frames 1-4.
• To solve this problem, the five-valued model of
  the D-algorithm was extended to be the
  nine-valued model
• Table 1 compares the five-valued and nine-valued
  models

19
Putzolu and Roth Test Method (2)
Table 1. Comparison of 5-valued and 9-valued
models
20
The nine-valued model

• The nine-valued model lets us use single-path
  sensitization in the D-algorithm.
• The nine-valued model is very inefficient during
  justification
• The nine-valued model has the following
  efficiency problems
• To justify an N-input gate's output value, there
  are NN choices
• No simple testability guidance can rank these NN
  choices.

21
Sequential Test Generator (STG2)

• Because of the efficiency problems in the
  previous test generators, a complete test
  generator STG2, without excessive memory
  requirements, is developed.
• Uses the Back Algorithm and the Split value model

22
The Back Algorithm (1)

• The Back Algorithm proceeds as follows
• the algorithm selects the primary output with the
  sensitized value
• this is accomplished through a new testability
  measurement called derivability
• the fault is not testable if no primary output
  can have a sensitized value
• the algorithm justifies the values required at
  the current time frame
• the test sequence has been found if the state
  input requirements of the current time frame
  match the initial state values

23
The Back Algorithm (2)

• Continued
• the back algorithm justifies time frame by time
  frame (all the requirements of one time frame can
  be handled simultaneously)
• during test generation, the circuit status has to
  contain at most two time frames the current and
  previous time frames.
• Hence, we can conclude the Back Algorithm's
  memory requirements is minimal.

24
Presentor Tarek Saad

• Fault simulation
• Sequential circuit fault simulation
• Nine-valued model
• Split value model
• Testability guidances

25
Fault Simulation

• Good machine
• A logic model of the circuit-under test without
  any faults inserted
• Faulty machines
• A logic model of the circuit-under-test with one
  or more fault models inserted
• Fault specification
• Defining the set of modeled faults and
  performing fault collapsing
• Fault insertion
• Selecting a subset of the faults to be simulated
  and creating the data structures to indicate the
  presence of the faults

26
Sequential Circuit Fault Simulation
Figure 4. Sequential circuit test simulation
model
27
Nine-valued Model (1)

• The good machine and bad machine are two
  independent sub-circuits with the same primary
  inputs.
• It combines the values of the two sub circuits to
  reduce memory needed to store circuit status.
• In this arrangement the two circuits must be
  justified simultaneously.

Figure 5. Realization of a Sequential circuit
Figure 6. The nine-valued model
28
Nine-valued Model (2)

• Inefficiencies
• Justifying two independent sub circuits
  simultaneously increases the number of backtracks
  and the time wasted.
• Split value algorithm will solve this problem.

29
Split Value Model (1)

• Extension to nine-value model to improve its
  performance during justification.
• It splits the nine values into two sets of three
  values for the good, and bad machine.
• Separate storage for the circuit statuses,
  good/bad machine can be justified separately.

Figure 7. The split value model
30
Split Value Model (2)

• Each machine is justified separately, we can use
  testability measurement of each circuit to rank
  available choices.
• Split model uses default value to reduce
  backtracks significantly.
• Definitions
• Good value. Value at the good machine.
• Bad value. Value at the bad machine.
• Relation. Relation between good and bad value.
• Good/bad values can be 0, 1, x(dont care), or
  z(high impedance).
• Sensitized lines. Lines with unequal good and
  bad values.
• Non-sensitized lines. Lines with equal good and
  bad value, not affected by fault site.
• Relation.Could be sensitized, non-sensitized, or
  unknown.

31
Split Value Model (3)

• Dynamic identification of relation information
  proceeds as follows
• If all input of an element are non sensitized
  lines, then all outputs must be non-sensitized.
• If any output of an element is a sensitized line,
  then at least one input must be a sensitized
  line.
• Advantages
• The high impedance value is used in bus element
  containing circuits to avoid bus conflicts.

32
Testability Guidance

• Two testability measurements guide decision
  making in conventional test generators
• Controllability measures the difficulty of
  placing a specific logic (0or1) value on that
  line.
• Observability measures.The difficulty of
  observing the fault effect at that line from the
  primary outputs.
• Both are calculated based on the good machine.
• Observability guides the sensitized-path
  selection while controllability guides the line
  value justification.
• Back algorithm (as mentioned) uses drivrablitiy
  similar to observabilityand measures the
  dificulty of driving the fault effect from the
  fault site to a line.

33
Presentor Rami Abielmona

• Experimental results
• STG2 Analysis
• Gentest Analysis
• Conclusions
• Future Work and Biographies

34
Experimental ResultsSequential Test Generators

• STG2 is an extension of STG1, described by
  Mallela and Wu
• STG2 uses the Back algorithm and the Split value
  model, while STG1 utilizes the extended backtrace
  method and the nine-valued model.
• STG1.5 uses the D-algorithm and the Split value
  model.
• From the experimental results that will be
  presented next, STG2 was chosen for
  implementation in Gentest, because it has shown
  the best fault coverage and total test-generation
  time.

35
Experimental ResultsSTG2 Analysis (1)

• The three sequential test generators were
  compared by live-testing them on a Convex C-1
  computer using a myriad of circuits, the latters
  characteristics shown in Table 2
• Looking at that table, a few definitions are in
  order
• Gates gtgtgt The number of gates in the circuit
• p1,p0 gtgtgt The primary inputs and outputs
• I/O pins gtgtgt Either input or output, but not
  both
• FF gtgtgt The number of flip-flops in the circuit
• Faults gtgtgt The number of faults in the circuit.

36
Experimental ResultsSTG2 Analysis (2)
Table 2. Characteristics of the circuits
Table 2. Characteristics of the circuits
37
Experimental ResultsSTG2 Analysis (3)

• Table 3 shows the detailed results of the
  analysis of STG2
• The definitions are as follows
• Time
• The sum of the test-generation time in seconds
  for all the target faults
• Detected/Untestable/Dropped
• The number of tests in each category
• Efficiency
• The sum of detected and untestable faults divided
  by the total faults.

38
Experimental ResultsSTG2 Analysis (4)
Table 3. Results for STG2
39
Experimental ResultsSTG2 Analysis (5)

• Table 4 compares efficiency and time for all
  three test generators.
• As we can see from the results, STG2 spent more
  time than STG1.5 for circuits c499 and c880, but
  overall, as the number of gates and faults in the
  circuit increase, the efficiency of STG2 is much
  higher than that of STG1.5, with a lower time
  factor as well.
• The latter observation leads us to the conclusion
  that test-generation overall time is much better
  using STG2, thus was chosen for incorporation in
  Gentest.

40
Experimental ResultsSTG2 Analysis (6)
Table 4. Comparison for STG1, STG1.5 and STG2
41
Experimental ResultsGentest Analysis (1)

• Another set of experiments were carried out on a
  Sun 3/60 workstation, using the Gentest test
  generation algorithm
• The set of circuits implemented this time vary
  from the previous ones, but still are represented
  by the same characteristics as the previous ones
  (See table 5, for a brief reference).

42
Experimental ResultsGentest Analysis (2)
Table 5. Characteristics of the circuits
43
Experimental ResultsGentest Analysis (3)

• Table 6 shows the detailed results of the
  analysis of Gentest
• The definitions are as follows
• Time
• The sum of the test-generation time,
  fault-simulation time and communication time
  between the CPU and the circuit in seconds for
  all the target faults
• Trial/Untestable/Sequences
• The number of tests or sequences in each
  category
• Vectors/Detected
• The number of vectors is the size of the final
  test sequence, while the detected column lists
  the faults detected by CSim
• Fault Coverage
• The sum of untestable faults identified by STG2
  and detected faults identified by Csim, divided
  by the total number of faults.

44
Experimental ResultsGentest Analysis (4)
Table 6. Results for Gentest
45
Experimental ResultsGentest Analysis (5)

• Observations of the results are as follows
• The number of sequences generated by STG2 is
  always much smaller than the faults detected by
  CSim
• The number of runs needed by STG2 to identify all
  the untestable faults cannot be reduced, hence is
  on the critical path of the total test-generation
  time
• The CPU time limit was set to two seconds per
  fault, thus for circuits logic6 and mickey,
  the fault coverage was very low due to the amount
  of target faults in these circuits and
• The total average fault coverage did increase as
  the Gentest algorithm was applied, as opposed to
  the results in table 3, which showed the circuits
  after STG2 alone was applied.

46
Paper Conclusions

• Gentest has proven to be a very efficient
  automatic test-generation system for sequential
  circuits
• It minimizes the total time needed for
  test-generation, as well as maximizes the
  efficiency
• Gentest also demonstrates an improved, but not
  ideal, test fault coverage

47
Future Work

• Future work on test-generation algorithms will
  concentrate on large functional units, and more
  complex circuitries
• To do so, the test-generation process has to be
  sped up, through the use of high-level models or
  functional units, such as instantiating
  behavioral models of a circuit (e.g. ALU, shift
  register, binary counter), rather than their
  gate- or even switch-level implementations
• Such an algorithm had not yet been well defined

48
Author Biographies