AT91 Hardware and Power considerations

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AT91 Hardware and Power considerations
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Power Supply considerations
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Powering the AT91 (1/3)

• Double Power Line (except for the AT91x40 family)
  
• I/O lines
• VDDIO
• Chip core
• VDDCORE
• Dedicated Power Lines
• Oscillator and PLL cells
• VDDPLL
• Analog peripherals ADC and DAC
• VDDA
• RTC, the 32768 Hz oscillator and the Shut-down
  Logic of the APMC
• VDDBU

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Powering the AT91 (2/3)

• Constraints
• VDDIO ? VDDCORE
• VDDPLL ? VDDCORE
• VDDA ? VDDCORE
• VDDIO and VDDCORE are separated to permit the I/O
  Lines to be powered with 5V, thus resulting in
  full TTL compliance.

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Powering the AT91 (3/3)

• Example AT91M55800A

Triple Supply with Shut Down Control
Memories
AT91M55800A
DC/DC Converter
3.3V
VDDIO
2.7V
VDDCORE
16MHz Crystal
Battery
VDDBU
32KHz Crystal
Level Shut Down Control Signal
Any kind of wake-up signal
SHDN
SHD
WAKEUP
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Reset considerations
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Resetting the AT91

• Two external reset inputs
• NRST microcontroller reset pin
• NTRST JTAG/ICE reset pin (not available on the
  AT91x40 family)
• Internal reset can also be generated by the
  watchdog and by software (EBI remap function
  allows dynamic reset vector)
• Reset sources

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Reset detection

• NRST is an active low-level input. It is asserted
  asynchronously but exit from reset is
  synchronized internally to the MCK.
• MCK must be active for a minimum of 10 clock
  cycles up to the rising edge of NRST
• External (NRST) or Internal (Watchdog) Reset
  Request
• Test the Reset Status Register
• in the Special Function Module
• If reads 0x6C Cause of Reset is External NRST
  Pin assertion
• If reads 0x53 Cause of Reset is Internal Reset
  from Watchdog

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Constraints on Reset and related signals (1/2)

• Tri-state mode
• To enter tri-state mode, the pin NTRI must be
  held low during the last 10 clock cycles before
  the rising edge of NRST
• For normal operation, the pin NTRI must be held
  during reset by a resistor of up to 400KOhm
• Boot Mode Select
• The input level on BMS pin during the last 10
  clock cycles before the rising edge of NRST
  selects the boot memory

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Constraints on Reset and related signals (2/2)

• JTAG/ICE Debug mode
• JTAGSEL pin is sampled at Power-Up
• The JTAG/ICE debug mode is enabled when JTAGSEL
  is low
• JTAG Boundary-scan is enabled when JTAGSEL is high

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Clock considerations
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Clock Connections (1/3)

• The AT91x40 Family, the AT91M63200 and the
  AT91M43300 have a MCKI input pin on which a
  crystal oscillator has to be connected.
• The AT91M42800A has 1 embedded oscillators
• The Slow Clock Oscillator
• It has been designed for use with a 32.768 kHz
  fundamental crystal,
• The oscillator integrates an equivalent load
  capacitance equal to 10 pF.

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Clock Connections (2/3)

• The AT91M55800A has 2 embedded oscillators
• The RTC Oscillator powered by the backup battery
  voltage supplied on the VDDBU pins.
• The XIN32 and XOUT32 pins must be connected to a
  32768 Hz crystal,
• The oscillator has been especially designed to
  connect to a 6 pF typical load capacitance
  crystal and does not require any external
  capacitor, as it integrates the XIN32 and XOUT32
  capacitors to ground
• For a higher typical load capacitance, two
  external capacitances must be wired.

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Clock Connections (3/3)

• The Main Oscillator, which provides a clock that
  depends on the frequency of the crystal connected
  to the XIN and XOUT pins
• The Main Oscillator is designed for a 3 to 20 MHz
  fundamental crystal,
• The oscillator contains 25 pF capacitances on
  each XIN and XOUT pin. Consequently, CL1 and CL2
  can be removed when a crystal with a load
  capacitance of 12.5 pF is used.

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Oscillator considerations
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Pierce oscillator

• The crystal manufacturer specifies the typical
  load capacitor,
• internal load capacitor external load
  capacitor stray capacitor must be equal to
  the specified load capacitor for the crystal.

C1int
C2int
Bias resistor
On-chip
XIN
XOUT
Crystal
On the board
C1ext
C2ext
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AT91M42800A Oscillator

• Slow Clock Oscillator
• Frequency running 32.768 kHz typical
• Maxi. current dissipation 9 µA
• Internal capacitance between Xin-GND or
  Xout-GND20 pF (per pin) or a Internal
  Equivalent Load Capacitance of 10 pF
• Start-up time 1.5 s (depends on the crystal
  quality)
• On-chip bias resistor

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AT91M55800A Oscillators (1/3)

• RTC Oscillator
• Frequency running 32.768 kHz typical
• Very Low Power Design less than 1 µA
• Internal capacitance between Xin-GND or
  Xout-GND12 pF (per pin) or a Internal
  Equivalent Load Capacitance of 6 pF
• Start-up time 700 ms (depends on the crystal
  quality)
• On-chip bias resistor
• The AT91M55800A starts from the slow clock
  source, this oscillator must always be
  implemented
• gt VDDBU must always be powered.

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AT91M55800A Oscillators (2/3)

• Main Oscillator
• Frequency running with large bandwidth 3 to 20
  MHz
• Low Power Design
• Internal capacitance between Xin-GND or
  Xout-GND25 pF (per pin) or a Internal
  Equivalent Load Capacitance of 12.5 pF
• Shutdown mode capability
• Bypass mode capability. In this state, the
  external clock must be fitted on Xin input. The
  input bandwidth is some kHz to 33 MHz.
• On-chip bias resistor

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AT91M55800A Oscillators (3/3)

• Startup Time
• Dedicated counter OSCOUNT in the Advanced Power
  Management Controller which indicates when the
  startup is finished.

(in ms)
(in MHz)
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PLL considerations
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AT91M42800A PLLs (1/2)

• One oscillator (Low Frequency)
• Two PLLs
• PLL A, which provides a low-to-middle frequency
  clock range
• PLL B, which provides a middle-to-high frequency
  range

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AT91M42800A PLLs (2/2)

• Two PLLs are integrated in the AT91M42800A in
  order to cover a larger frequency range.
• Both PLLs have a dedicated pin (PLLRCA or PLLRCB)
  which must be connected with an appropriate
  second order filter made up of one resistor and
  two capacitors.
• Dedicated counter PLLCOUNT in the Power
  Management Controller which indicates when the
  transient state is finished (settling time).

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AT91M55800A PLL (1/2)

• Two oscillators
• Slow Clock Oscillator
• Main Oscillator
• One PLL to reach the maximum clock frequency

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AT91M55800A PLL (2/2)

• Multiply the Main Oscillator frequency by a
  number up to 64 to reach the maximum frequency.
• Dedicated PLLRC pin which must be connected with
  an appropriate second order filter made up of one
  resistor and two capacitors.
• Dedicated counter PLLCOUNT in the Advanced Power
  Management Controller which indicates when the
  transient state is finished (settling time).

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PLL Settling time

• Necessary time to reach stable state
  (overshooting frequency lt 10 of the target
  frequency)

(in ms)
(in MHz)
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