CMPUT429/CMPE382 Winter 2001

1
CMPUT429/CMPE382 Winter 2001

• Topic4 Memory Hierarchy
• (Adapted from David A. Pattersons CS252
• lecture slides at Berkeley)

2
Recap Who Cares About the Memory Hierarchy?
Processor-DRAM Memory Gap (latency)
µProc 60/yr. (2X/1.5yr)
1000
CPU
Moores Law
100
Processor-Memory Performance Gap(grows 50 /
year)
Performance
10
DRAM 9/yr. (2X/10 yrs)
DRAM
1
1980
1981
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
1982
Time
3
Levels of the Memory Hierarchy
Upper Level
Capacity Access Time Cost
Staging Xfer Unit
faster
CPU Registers 100s Bytes lt1s ns
Registers
prog./compiler 1-8 bytes
Instr. Operands
Cache 10s-100s K Bytes 1-10 ns 10/ MByte
Cache
cache cntl 8-128 bytes
Blocks
Main Memory M Bytes 100ns- 300ns 1/ MByte
Memory
OS 512-4K bytes
Pages
Disk 10s G Bytes, 10 ms (10,000,000 ns) 0.0031/
MByte
Disk
user/operator Mbytes
Files
Larger
Tape infinite sec-min 0.0014/ MByte
Tape
Lower Level
4
The Principle of Locality

• The Principle of Locality
• Program access a relatively small portion of the
  address space at any instant of time.
• Two Different Types of Locality
• Temporal Locality (Locality in Time) If an item
  is referenced, it will tend to be referenced
  again soon (e.g., loops, reuse)
• Spatial Locality (Locality in Space) If an item
  is referenced, items whose addresses are close by
  tend to be referenced soon (e.g., straightline
  code, array access)
• Last 15 years, HW (hardware) relied on locality
  for speed

5
Memory Hierarchy Terminology

• Hit data appears in some block in the upper
  level (example Block X)
• Hit Rate the fraction of memory access found in
  the upper level
• Hit Time Time to access the upper level which
  consists of
• RAM access time Time to determine hit/miss
• Miss data needs to be retrieve from a block in
  the lower level (Block Y)
• Miss Rate 1 - (Hit Rate)
• Miss Penalty Time to replace a block in the
  upper level
• Time to deliver the block to the processor
• Hit Time ltlt Miss Penalty (500 instructions on
  21264!)

6
Cache Measures

• Hit rate fraction found in that level
• So high that usually talk about Miss rate
• Miss rate fallacy miss rate does not predict
  average memory access time in memory.
• Average memory-access time Hit time Miss
  rate x Miss penalty (ns or clocks)
• Miss penalty time to replace a block from lower
  level, including time to replace in CPU
• access time time to lower level
• f(latency to lower level)
• transfer time time to transfer block
• f(BW between upper lower levels)

7
Generations of Microprocessors

• Time of a full cache miss in instructions
  executed
• 1st Alpha 340 ns/5.0 ns  68 clks x 2 or 136
• 2nd Alpha 266 ns/3.3 ns  80 clks x 4 or 320
• 3rd Alpha 180 ns/1.7 ns 108 clks x 6 or 648

8
Simplest Cache Direct Mapped
Memory Address
Memory
0
4 Byte Direct Mapped Cache
1
Cache Index
2
0
3
1
4
2
5
3
6

• Location 0 can be occupied by data from
• Memory location 0, 4, 8, ... etc.
• In general any memory locationwhose 2 LSBs of
  the address are 0s
• Addresslt10gt gt cache index
• Which one should we place in the cache?
• How can we tell which one is in the cache?

7
8
9
A
B
C
D
E
F
9
1 KB Direct Mapped Cache, 32B blocks

• For a 2 N byte cache
• The uppermost (32 - N) bits are always the Cache
  Tag
• The lowest M bits are the Byte Select (Block Size
  2 M)

0
4
31
9
Cache Index
Cache Tag
Byte Select
Example 0x50
Ex 0x01
Ex 0x00
Cache Tag is Stored as part of the cache state
Cache Data
Valid Bit
Cache Tag

0
Byte 0
Byte 1
Byte 31

1
0x50
Byte 32
Byte 33
Byte 63
2
3




31
Byte 992
Byte 1023
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Two-way Set Associative Cache

• N-way set associative N entries for each Cache
  Index
• N direct mapped caches operates in parallel (N
  typically 2 to 4)
• Example Two-way set associative cache
• Cache Index selects a set from the cache
• The two tags in the set are compared in parallel
• Data is selected based on the tag result

Cache Index
Cache Data
Cache Tag
Valid
Cache Block 0



Adr Tag
Compare
0
1
Mux
Sel1
Sel0
OR
Cache Block
Hit
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Disadvantage of Set Associative Cache

• N-way Set Associative Cache v. Direct Mapped
  Cache
• N comparators vs. 1
• Extra MUX delay for the data
• Data comes AFTER Hit/Miss
• In a direct mapped cache, Cache Block is
  available BEFORE Hit/Miss
• Possible to assume a hit and continue. Recover
  later if miss.

12
Review Cache performance
13
Impact on Performance

• Suppose a processor executes at
• Clock Rate 1 GHz (1 ns per cycle), Ideal (no
  misses) CPI 1.1
• 50 arith/logic, 30 ld/st, 20 control
• Suppose that 10 of memory operations get 100
  cycle miss penalty
• Suppose that 1 of instructions get same miss
  penalty

78 of the time the proc is stalled waiting for
memory!
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Example Harvard Architecture

• Unified vs Separate ID (Harvard)
• Table on page 384
• 16KB ID Inst miss rate0.64, Data miss
  rate6.47
• 32KB unified Aggregate miss rate1.99
• Which is better (ignore L2 cache)?
• Assume 33 data ops ? 75 accesses from
  instructions (1.0/1.33)
• hit time1, miss time50
• Note that data hit has 1 stall for unified cache
  (only one port)
• AMATHarvard75x(10.64x50)25x(16.47x50)
  2.05
• AMATUnified75x(11.99x50)25x(111.99x50)
  2.24

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4 Questions for Memory Hierarchy

• Q1 Where can a block be placed in the upper
  level? (Block placement)
• Q2 How is a block found if it is in the upper
  level? (Block identification)
• Q3 Which block should be replaced on a miss?
  (Block replacement)
• Q4 What happens on a write? (Write strategy)

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Q1 Where can a block be placed in the upper
level?

• Block 12 placed in 8 block cache
• Fully associative, direct mapped, 2-way set
  associative
• S.A. Mapping Block Number Modulo Number Sets

Direct Mapped (12 mod 8) 4
2-Way Assoc (12 mod 4) 0
Full Mapped
Cache
Memory
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Q2 How is a block found if it is in the upper
level?

• Tag on each block
• No need to check index or block offset
• Increasing associativity shrinks index, expands
  tag

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Q3 Which block should be replaced on a miss?

• Easy for Direct Mapped
• Set Associative or Fully Associative
• Random
• LRU (Least Recently Used)
• Assoc 2-way 4-way 8-way
• Size LRU Ran LRU Ran
  LRU Ran
• 16 KB 5.2 5.7 4.7 5.3 4.4 5.0
• 64 KB 1.9 2.0 1.5 1.7 1.4 1.5
• 256 KB 1.15 1.17 1.13 1.13 1.12
  1.12

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Q4 What happens on a write?

• Write throughThe information is written to both
  the block in the cache and to the block in the
  lower-level memory.
• Write backThe information is written only to the
  block in the cache. The modified cache block is
  written to main memory only when it is replaced.
• is block clean or dirty?
• Pros and Cons of each?
• WT read misses cannot result in writes
• WB no repeated writes to same location
• WT always combined with write buffers so that
  dont wait for lower level memory

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Write Buffer for Write Through

• A Write Buffer is needed between the Cache and
  Memory
• Processor writes data into the cache and the
  write buffer
• Memory controller write contents of the buffer
  to memory
• Write buffer is just a FIFO
• Typical number of entries 4
• Works fine if Store frequency (w.r.t. time) ltlt
  1 / DRAM write cycle
• Memory system designers nightmare
• Store frequency (w.r.t. time) -gt 1 / DRAM
  write cycle
• Write buffer saturation

21
Review 4/4 TLB, Virtual Memory

• Caches, TLBs, Virtual Memory all understood by
  examining how they deal with 4 questions 1)
  Where can block be placed? 2) How is block found?
  3) What block is repalced on miss? 4) How are
  writes handled?
• Page tables map virtual address to physical
  address
• TLBs make virtual memory practical
• Locality in data gt locality in addresses of
  data, temporal and spatial
• TLB misses are significant in processor
  performance
• funny times, as most systems cant access all of
  2nd level cache without TLB misses!
• Today VM allows many processes to share single
  memory without having to swap all processes to
  disk today VM protection is more important than
  memory hierarchy

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Review Improving Cache Performance

• 1. Reduce the miss rate,
• 2. Reduce the miss penalty, or
• 3. Reduce the time to hit in the cache.

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Reducing Misses

• Classifying Misses 3 Cs
• CompulsoryThe first access to a block is not in
  the cache, so the block must be brought into the
  cache. Also called cold start misses or first
  reference misses.(Misses in even an Infinite
  Cache)
• CapacityIf the cache cannot contain all the
  blocks needed during execution of a program,
  capacity misses will occur due to blocks being
  discarded and later retrieved.(Misses in Fully
  Associative Size X Cache)
• ConflictIf block-placement strategy is set
  associative or direct mapped, conflict misses (in
  addition to compulsory capacity misses) will
  occur because a block can be discarded and later
  retrieved if too many blocks map to its set. Also
  called collision misses or interference
  misses.(Misses in N-way Associative, Size X
  Cache)
• More recent, 4th C
• Coherence - Misses caused by cache coherence.

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3Cs Absolute Miss Rate (SPEC92)
Conflict
Compulsory vanishingly small
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21 Cache Rule
miss rate 1-way associative cache size X
miss rate 2-way associative cache size X/2
Conflict
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3Cs Relative Miss Rate
Conflict
Flaws for fixed block size Good insight gt
invention
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How Can Reduce Misses?

• 3 Cs Compulsory, Capacity, Conflict
• In all cases, assume total cache size not
  changed
• What happens if
• 1) Change Block Size Which of 3Cs is obviously
  affected?
• 2) Change Associativity Which of 3Cs is
  obviously affected?
• 3) Change Compiler Which of 3Cs is obviously
  affected?

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1. Reduce Misses via Larger Block Size
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2. Reduce Misses via Higher Associativity

• 21 Cache Rule
• Miss Rate DM cache size N Miss Rate 2-way cache
  size N/2
• Beware Execution time is only final measure!
• Will Clock Cycle time increase?
• Hill 1988 suggested hit time for 2-way vs.
  1-way external cache 10, internal 2

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Example Avg. Memory Access Time vs. Miss Rate

• CCT Clock Cycle Time
• Example
• Assume that
• CCT(2-way) 1.10 CCT(1-way)
• CCT(4-way) 1.12 CCT(1-way)
• CCT(8-way) 1.14 CCT(1-way)

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Example Avg. Memory Access Time vs. Miss Rate
(cont.)

• Cache
• Size Associativity
• (KB) 1-way 2-way 4-way 8-way
• 1 2.33 2.15 2.07 2.01
• 2 1.98 1.86 1.76 1.68
• 4 1.72 1.67 1.61 1.53
• 8 1.46 1.48 1.47 1.43
• 16 1.29 1.32 1.32 1.32
• 32 1.20 1.24 1.25 1.27
• 64 1.14 1.20 1.21 1.23
• 128 1.10 1.17 1.18 1.20
• Miss Rate for each cache size/organization (Red
  means A.M.A.T. not improved by more associativity)

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3. Reducing Misses via aVictim Cache

• How to combine fast hit time of direct mapped
  yet still avoid conflict misses?
• Add buffer to place data discarded from cache
• Jouppi 1990 4-entry victim cache removed 20
  to 95 of conflicts for a 4 KB direct mapped data
  cache
• Used in Alpha, HP machines

DATA
TAGS
One Cache line of Data
Tag and Comparator
One Cache line of Data
Tag and Comparator
One Cache line of Data
Tag and Comparator
One Cache line of Data
Tag and Comparator
To Next Lower Level In
Hierarchy
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4. Reducing Misses via Pseudo-Associativity

• How to combine fast hit time of Direct Mapped and
  have the lower conflict misses of 2-way
  associative cache?
• Divide cache on a miss, check other half of
  cache to see if the data is there, if so have a
  pseudo-hit (slow hit)
• Drawback Difficult to build a CPU pipeline if
  hit may take either 1 or 2 cycles
• Better for caches not tied directly to processor
  (L2)
• Used in MIPS R1000 L2 cache, similar in UltraSPARC

Hit Time
Miss Penalty
Pseudo Hit Time
Time
34
5. Reducing Misses by Hardware Prefetching of
Instructions Data

• E.g., Instruction Prefetching
• Alpha 21064 fetches 2 blocks on a miss
• Extra block placed in stream buffer
• On miss check stream buffer
• New IBM POWER4 has 8 data prefetch streams
• Works with data blocks too
• Jouppi 1990 1 data stream buffer got 25 misses
  from 4KB cache 4 streams got 43
• Palacharla Kessler 1994 for scientific
  programs for 8 streams got 50 to 70 of misses
  from 2 64KB, 4-way set associative caches
• Prefetching relies on having extra memory
  bandwidth that can be used without penalty

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6. Reducing Misses by Software Prefetching Data

• Data Prefetch
• Load data into register (HP PA-RISC loads)
• Cache Prefetch load into cache (MIPS IV,
  PowerPC, SPARC v. 9)
• Nonfaulting prefetching instructions cannot cause
  faults. They are a form of speculative execution.
• Prefetching comes in two flavors
• Binding prefetch Requests load directly into
  register.
• Must be correct address and register!
• Non-Binding prefetch Load into cache.
• Can be incorrect. Frees HW/SW to guess!
• Issuing Prefetch Instructions takes time
• Is cost of prefetch issues lt savings in reduced
  misses?
• Higher superscalar reduces difficulty of issue
  bandwidth

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7. Reducing Misses by Compiler Optimizations

• McFarling 1989 reduced caches misses by 75 on
  8KB direct mapped cache, 4 byte blocks in
  software
• Instructions
• Reorder procedures in memory to reduce conflict
  misses
• Profiling to examine conflicts (using tools they
  developed)
• Data
• Merging Arrays improve spatial locality by
  single array of compound elements vs. 2 arrays
• Loop Interchange change nesting of loops to
  access data in order stored in memory
• Loop Fusion Combine 2 independent loops that
  have same looping and some variables overlap
• Blocking Improve temporal locality by accessing
  blocks of data repeatedly vs. going down whole
  columns or rows

37
Merging Arrays Example

• / Before 2 sequential arrays /
• int valSIZE
• int keySIZE
• / After 1 array of structures /
• struct merge
• int val
• int key
• struct merge merged_arraySIZE
• Reducing conflicts between val key improve
  spatial locality

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Loop Interchange Example

• / Before /
• for (k 0 k lt 100 k k1)
• for (j 0 j lt 100 j j1)
• for (i 0 i lt 5000 i i1)
• xij 2 xij
• / After /
• for (k 0 k lt 100 k k1)
• for (i 0 i lt 5000 i i1)
• for (j 0 j lt 100 j j1)
• xij 2 xij
• Sequential accesses instead of striding through
  memory every 100 words improved spatial locality

39
Loop Fusion Example

• / Before /
• for (i 0 i lt N i i1)
• for (j 0 j lt N j j1)
• aij 1/bij cij
• for (i 0 i lt N i i1)
• for (j 0 j lt N j j1)
• dij aij cij
• / After /
• for (i 0 i lt N i i1)
• for (j 0 j lt N j j1)
• aij 1/bij cij
• dij aij cij
• 2 misses per access to a c vs. one miss per
  access improve spatial locality

40
Blocking Example

• / Before /
• for (i 0 i lt N i i1)
• for (j 0 j lt N j j1)
• r 0
• for (k 0 k lt N k k1)
• r r yikzkj
• xij r
• Two Inner Loops
• Read all NxN elements of z
• Read N elements of 1 row of y repeatedly
• Write N elements of 1 row of x
• Capacity Misses a function of N Cache Size
• 2N3 N2 gt (assuming no conflict otherwise )
• Idea compute on BxB submatrix that fits

41
Blocking Example

• / After /
• for (jj 0 jj lt N jj jjB)
• for (kk 0 kk lt N kk kkB)
• for (i 0 i lt N i i1)
• for (j jj j lt min(jjB-1,N) j j1)
• r 0
• for (k kk k lt min(kkB-1,N) k k1)
• r r yikzkj
• xij xij r
• B called Blocking Factor
• Capacity Misses from 2N3 N2 to N3/B2N2
• Conflict Misses Too?

42
Reducing Conflict Misses by Blocking

• Conflict misses in caches not FA vs. Blocking
  size
• Lam et al 1991 a blocking factor of 24 had a
  fifth the misses vs. 48 despite both fit in cache

43
Summary of Compiler Optimizations to Reduce Cache
Misses (by hand)
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Summary Miss Rate Reduction

• 3 Cs Compulsory, Capacity, Conflict
• 1. Reduce Misses via Larger Block Size
• 2. Reduce Misses via Higher Associativity
• 3. Reducing Misses via Victim Cache
• 4. Reducing Misses via Pseudo-Associativity
• 5. Reducing Misses by HW Prefetching Instr, Data
• 6. Reducing Misses by SW Prefetching Data
• 7. Reducing Misses by Compiler Optimizations
• Prefetching comes in two flavors
• Binding prefetch Requests load directly into
  register.
• Must be correct address and register!
• Non-Binding prefetch Load into cache.
• Can be incorrect. Frees HW/SW to guess!

45
Review Improving Cache Performance

• 1. Reduce the miss rate,
• 2. Reduce the miss penalty, or
• 3. Reduce the time to hit in the cache.

46
Write PolicyWrite-Through vs Write-Back

• Write-through all writes update cache and
  underlying memory/cache
• Can always discard cached data - most up-to-date
  data is in memory
• Cache control bit only a valid bit
• Write-back all writes simply update cache
• Cant just discard cached data - may have to
  write it back to memory
• Cache control bits both valid and dirty bits
• Other Advantages
• Write-through
• memory (or other processors) always have latest
  data
• Simpler management of cache
• Write-back
• much lower bandwidth, since data often
  overwritten multiple times
• Better tolerance to long-latency memory?

47
Write Policy 2Write Allocate vs
Non-Allocate(What happens on write-miss)

• Write allocate allocate new cache line in cache
• Usually means that you have to do a read miss
  to fill in rest of the cache-line!
• Alternative per/word valid bits
• Write non-allocate (or write-around)
• Simply send write data through to underlying
  memory/cache - dont allocate new cache line!

48
1. Reducing Miss Penalty Read Priority over
Write on Miss
Write Buffer
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1. Reducing Miss Penalty Read Priority over
Write on Miss

• Write-through with write buffers causes RAW
  conflicts with main memory reads on cache misses
• If simply wait for write buffer to empty, might
  increase read miss penalty (old MIPS 1000 by 50
  )
• Check write buffer contents before read if no
  conflicts, let the memory access continue
• Write-back also want buffer to hold misplaced
  blocks
• Read miss replacing dirty block
• Normal Write dirty block to memory, and then do
  the read
• Instead copy the dirty block to a write buffer,
  then do the read, and then do the write
• CPU stall less since restarts as soon as do read

50
2. Reduce Miss Penalty Early Restart and
Critical Word First

• Dont wait for full block to be loaded before
  restarting CPU
• Early restartAs soon as the requested word of
  the block arrives, send it to the CPU and let
  the CPU continue execution
• Critical Word FirstRequest the missed word first
  from memory and send it to the CPU as soon as it
  arrives let the CPU continue execution while
  filling the rest of the words in the block. Also
  called wrapped fetch and requested word first
• Generally useful only in large blocks,
• Spatial locality a problem tend to want next
  sequential word, so not clear if benefit by early
  restart

block
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3. Reduce Miss Penalty Non-blocking Caches to
reduce stalls on misses

• Non-blocking cache or lockup-free cache allow
  data cache to continue to supply cache hits
  during a miss
• requires F/E bits on registers or out-of-order
  execution
• requires multi-bank memories
• hit under miss reduces the effective miss
  penalty by working during miss vs. ignoring CPU
  requests
• hit under multiple miss or miss under miss
  may further lower the effective miss penalty by
  overlapping multiple misses
• Significantly increases the complexity of the
  cache controller as there can be multiple
  outstanding memory accesses
• Requires muliple memory banks (otherwise cannot
  support)
• Penium Pro allows 4 outstanding memory misses

52
Value of Hit Under Miss for SPEC
0-gt1 1-gt2 2-gt64 Base
Hit under n Misses

• FP programs on average AMAT 0.68 -gt 0.52 -gt
  0.34 -gt 0.26
• Int programs on average AMAT 0.24 -gt 0.20 -gt
  0.19 -gt 0.19
• 8 KB Data Cache, Direct Mapped, 32B block, 16
  cycle miss

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4 Add a second-level cache

• L2 Equations
• AMAT Hit TimeL1 Miss RateL1 x Miss
  PenaltyL1
• Miss PenaltyL1 Hit TimeL2 Miss RateL2 x Miss
  PenaltyL2
• AMAT Hit TimeL1
• Miss RateL1 x (Hit TimeL2 Miss RateL2
  Miss PenaltyL2)
• Definitions
• Local miss rate misses in this cache divided by
  the total number of memory accesses to this cache
  (Miss rateL2)
• Global miss ratemisses in this cache divided by
  the total number of memory accesses generated by
  the CPU (Miss RateL1 x Miss RateL2)
• Global Miss Rate is what matters

54
Comparing Local and Global Miss Rates

• 32 KByte 1st level cacheIncreasing 2nd level
  cache
• Global miss rate close to single level cache rate
  provided L2 gtgt L1
• Dont use local miss rate
• L2 not tied to CPU clock cycle!
• Cost A.M.A.T.
• Generally Fast Hit Times and fewer misses
• Since hits are few, target miss reduction

Linear
Cache Size
Log
Cache Size
55
Reducing Misses Which apply to L2 Cache?

• Reducing Miss Rate
• 1. Reduce Misses via Larger Block Size
• 2. Reduce Conflict Misses via Higher
  Associativity
• 3. Reducing Conflict Misses via Victim Cache
• 4. Reducing Conflict Misses via
  Pseudo-Associativity
• 5. Reducing Misses by HW Prefetching Instr, Data
• 6. Reducing Misses by SW Prefetching Data
• 7. Reducing Capacity/Conf. Misses by Compiler
  Optimizations

56
L2 cache block size A.M.A.T.

• 32KB L1, 8 byte path to memory

57
Reducing Miss Penalty Summary

• Four techniques
• Read priority over write on miss
• Early Restart and Critical Word First on miss
• Non-blocking Caches (Hit under Miss, Miss under
  Miss)
• Second Level Cache
• Can be applied recursively to Multilevel Caches
• Danger is that time to DRAM will grow with
  multiple levels in between
• First attempts at L2 caches can make things
  worse, since increased worst case is worse

58
What is the Impact of What Youve Learned About
Caches?

• 1960-1985 Speed ƒ(no. operations)
• 1990
• Pipelined Execution Fast Clock Rate
• Out-of-Order execution
• Superscalar Instruction Issue
• 1998 Speed ƒ(non-cached memory accesses)
• Superscalar, Out-of-Order machines hide L1 data
  cache miss (5 clocks) but not L2 cache miss
  (50 clocks)?

59
Cache Optimization Summary

• Technique MR MP HT Complexity
• Larger Block Size 0Higher
  Associativity 1Victim Caches 2Pseudo-As
  sociative Caches 2HW Prefetching of
  Instr/Data 2Compiler Controlled
  Prefetching 3Compiler Reduce Misses 0
• Priority to Read Misses 1Early Restart
  Critical Word 1st 2Non-Blocking
  Caches 3Second Level Caches 2

miss rate
miss penalty
60
A Modern Memory Hierarchy

• By taking advantage of the principle of locality
• Present the user with as much memory as is
  available in the cheapest technology.
• Provide access at the speed offered by the
  fastest technology.

61
Summary Caches

• The Principle of Locality
• Program access a relatively small portion of the
  address space at any instant of time.
• Temporal Locality Locality in Time
• Spatial Locality Locality in Space
• Three Major Categories of Cache Misses
• Compulsory Misses sad facts of life. Example
  cold start misses.
• Capacity Misses increase cache size
• Conflict Misses increase cache size and/or
  associativity.
• Write Policy
• Write Through needs a write buffer.
• Write Back control can be complex
• Today CPU time is a function of (ops, cache
  misses) vs. just f(ops) What does this mean to
  Compilers, Data structures, Algorithms?

62
Summary The Cache Design Space

• Several interacting dimensions
• cache size
• block size
• associativity
• replacement policy
• write-through vs write-back
• The optimal choice is a compromise
• depends on access characteristics
• workload
• use (I-cache, D-cache, TLB)
• depends on technology / cost
• Simplicity often wins

Cache Size
Associativity
Block Size
Bad
Factor A
Factor B
Good
Less
More
63
IBM POWER4 Memory Hierarchy
4 cycles to load to a floating point
register 128-byte blocks divided into 32-byte
sectors
L1(Instr.) 64 KB Direct Mapped
L1(Data) 32 KB 2-way, FIFO
write allocate 14 cycles to load to a
floating point register 128-byte blocks
L2(Instr. Data) 1440 KB, 3-way,
pseudo-LRU (shared by two processors)
L3(Instr. Data) 128 MB 8-way (shared by two
processors)
? 340 cycles 512-byte blocks divided into
128-byte sectors
64
Intel Itanium Processor
L1(Data) 16 KB, 4-way dual-ported write through
L1(Instr.) 16 KB 4-way
32-byte blocks 2 cycles
64-byte blocks write allocate 12 cycles
L2 (Instr. Data) 96 KB, 6-way
4 MB (on package, off chip)
64-byte blocks 128 bits bus at 800 MHz (12.8
GB/s) 20 cycles
65
Future Intel McKinley Processor
L1(Data) 16 KB, 4-way dual-ported write through
L1(Instr.) 16 KB 4-way
32-byte blocks 1 cycle
64-byte blocks write allocate 6 cycles
L2 (Instr. Data) 256 KB, 6-way
L3 (Instr. Data) 3 MB (on chip)
64-byte blocks 32 GB/s 12 cycles