XTRP Software

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XTRP Software

• Nathan Eddy
• University of Illinois
• 2/24/00

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XTRP Software

• All software developed using CDFVME framework
• Java client side code
• C server side code
• Board Software - Clock board, Data board
• Test Software - Expert Panel, LoopTest Panel
• All the software is contained in the xtrp
  xtrpdaq packages which are both available in the
  CVS repository

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XTRP Clock Board

• Provides GUI for Clock board features
• Select input source
• Options for CDF clock
• Delays
• Mode
• Continuous for normal running
• Burst for debugging
• Ability to step the VME clock

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XTRP Data Board

• Basic Operating Parameters
• Mode Register
• Run - standard operation with full speed clocks
• Simulation - standard operation with VME
  controlled clock
• Configure - enable board to configure lookup RAM
• Parameters for Pipe Algorithms
• Force Hit Bits
• Disable Zero Crack
• Enable Error Masks
• Set the delay for track data stored in the Pipes

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XTRP Data Board

• Panel to control downloading of the 10 FPGAs
• Select which FPGAs to load as well as the file to
  load into them
• For the pipes, several standard algorithms can be
  selected
• Pipe - actual running
• Check Xftin - input test diagnostics

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XTRP Data Board

• Memory tests
• Parameters determine size and pattern of data
  written into RAMs
• Single segment tests
• Full segment tests
• Visual report of status for each segment
• Option to generate a log file with pass/fail
  reports for each segment

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XTRP Data Board

• Data board Simulator
• Java object which completely simulates the
  functionality of the Data Board
• Essential in debugging the Data Board
• Resides in the xtrp package

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XTRP Test Software

• Software developed primarily for testing and
  debugging the Data board
• Expert Panel - provides methods to micro diagnose
  data as it travels through the system
• LoopTest Panel - provides methods to run large
  amounts of data through the system at full speed

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XTRP Tests
Clock edges
Clock Board
Data Board
VME write to step clock
VME read compare to Simulator
VME write data into Pipes
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XTRP Expert Panel

• Interfaces with Clock board, Data board, and
  Simulation
• Initialization
• Clock control
• Lookup RAM
• Control
• Input selection
• Execute clocks
• Status displays
• Clocks
• Simulator Data board agreement

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CAL/MUON Data Flow
Pipe FPGAs
Segment RAMs
RAM Output
INPUT
Stage 0 segment output ORd
Stage 1 merge with adjacent wedges
Stage 2 latch output
OUTPUT
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XTRP Expert Panel

• The first step in the track extrapolation is
  decoding incoming tracks and presenting them to
  segment RAMs
• The address subpanel compares the decoded address
  presented to each segment to that expected by the
  Simulator

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XTRP Expert Panel

• The output of each side of the segment RAM is
  also checked against the Simulator
• LC refers to CMU side
• LI refers to IMU/CAL side

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XTRP Expert Panel

• At Stage 0, the output for each segment is input
  into a set of GTLs whose output is ORd
• It is possible to enable whether a given segment
  contributes to ORd output
• Each segment is again verified against the
  Simulator

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XTRP Expert Panel

• At Stage 1, the Stage 0 data is merged with data
  from adjacent wedges
• For diagnostic purposes, it is possible to force
  the Stage 1 output to a particular value

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XTRP Expert Panel

• At Stage 2, the data for a given wedge is latched
  onto the output buss to the transition module
• Again, it is possible to ignore Stage 1 data and
  output a particular value

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XTRP LoopTest Panel

• The LoopTest Panel provides methods to run data
  through the system at full speed from various
  sources
• It is able to interface with a Testclock,
  Linkertester boards, Linker boards as well as the
  Clock board and Data boards

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XTRP LoopTest Panel

• Input Tests
• Run data patterns from Linker output formatters
  into Data board Pipe FPGAs
• Send 250 clocks of data per test and verify it
  arrived
• Sent100 million clocks of data into the board
  without error
• Data Tests
• Run data from either Linker output formatters
  (250 clocks) or Linker-testerboard (10k clocks)
• Muon and Calorimetry output is captured in
  Linkertester Fifos and compared to expected
  output from the Simulator

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XTRP Tests
DATA TEST
Linker(2) Output Formatters
VME write
VME read compare to Simulation
Data transferred at full speed for 250 clocks
VME read from Pipe FPGAs
Linkertester Input Fifos
Data Board
CAL/MUON Data
INPUT TEST
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XTRP Tests
VME write
Output Fifos
Linkers (2)
Linkertesters (2)
Data transferred at full speed for 10k clocks
VME read compare to Simulation
Data Board
Input Fifos
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XTRP Tests
VME write
Output Fifos
Linkertester
Data Board
Data transferred at full speed for 10k clocks
VME read compare to Simulation
Input Fifos
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Future XTRP Software

• Revamping LoopTest software to add some features
  such as threading and a cleaner user interface
• Next big step will be migrating software to B0
  for use in integration testing