ELEC 327 Final Presentation

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• ELEC 327 Final Presentation
• Tate Hornbeck, Jon Stanley
• April 2008

2
Overall Concept

• Treat the course as a combination of smaller and
  standardized routes.
• This method allows us to change the overall
  course on the fly without recompiling every small
  change in Verilog
• Our system was inspired by the Logo/Turtle
  graphics programming language

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Logo/Turtle

• Graphics Language
• Uses simple move and draw instructions
• Forward x units
• Back x units
• Turn x degrees
• Pen up
• Pen down
• Etc.

4
Our Instruction Set

• Data Mnemonic
• 0000 NOP (0 sec)
• 0001 FWD 1 (1ft)
• 0010 FWD 2
• 0011 FR45 (45º)
• 0100 FL45
• 0101 FR90 (90º)
• 0110 FL90
• 0111 NOP 2 (500mS)

Data Mnemonic 1000 NOP 3 (1 sec) 1001 REV
1 1010 REV 2 1011 RR45 1100 RL45 1101
RR90 1110 RL90 1111 HALT CPU
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System Overview
RAM programmed with instructions
System Module (FSM)
Move Module
Monostable
Outputs RC control signals
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System Module

• Top Level Module
• Establishes the inputs as the data buttons and
  switches
• Switches 1 6 for RAM address
• Switches 7 8, buttons 1 2 are data inputs
• Button 3 sets Program/Run mode
• Button 4 writes data to RAM
• Button 5 resets PCR, HALT flag and resumes CPU
  operation to run instructions again.
• Contains the model of the FSM and RAM
• 64 instruction memory 4-bits

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Finite State Machine (FSM)

• Fetch
• RAM data stored to Instruction Register
• Program Counter Register increments
• Execute
• If CPU in RUN mode and HALT flag not set then
  send enable signal to Move module
• IR contents passed to Move module
• Pend
• Motion takes longer than instruction processing.
• FSM waits until Move module is finished before
  fetching next instruction

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Move Module

• Converts 4-bit instruction representation to
  desired RC car motion by controlling input and
  output multiplexers.
• Input multiplexer switches hard-coded bits of
  motion time to the Monostable module.
• Output multiplexer enabled/disabled by Monostable
  module output. When enabled, hard-coded bits of
  desired motion sent to output to remote control.

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Monostable Module

• Represents digitally controlled monostable
• Inputs
• Trigger (ignored when output is 1, posedge)
• Period (8-bits)
• Output
• 1 for given time period after trigger goes high
• 0 otherwise
• Contains modified clock divider module from lab
  to produce slower clock. Slow clock output has
  duty cycle of one clock cycle from Cout of
  divider (not 50 duty) to simplify logic in
  monostable.

10
Car Route
Finish
Our strategy for completing the course is to make
the fewest possible number of turns. We found
that turning is the most inconsistent car
command. This is our planned course.
Start
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The Programmed Course
Address Data Mnemonic 000000 0011
FR45 000001 0111 NOP 2 (500mS) 000010
0010 FWD 2 (2 feet) 000011 0010 FWD
2 000100 0111 NOP 2 000101 0110
FL90 000110 0111 NOP 2 000111 0010
FWD 2 001000 0010 FWD 2 001001 0111
NOP 2 001010 0101 FR90 001011 0111
NOP 2 001100 0010 FWD 2 001101 0111
NOP 2 001110 0010 FWD 2 001111 0111
NOP 2 010000 0001 FWD 1 010001 1111
HALT CPU
Finish
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
PCR
CPU HALT
Start
PCR
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Problems and Observations

• The problem that we experienced the most was the
  inconsistency with the car.
• Sometimes it would run perfectly and then the
  next time it would drive straight into a chair.
• Another issue we noticed was that as the
  batteries died, the cars reponse was slower,
  thus changing the timing for turns and such.
• Movement errors due to car and environment
  accumulate over distance and cannot be corrected
  without sensors.

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Problems and Observations

• Instructions for all motions are relatively
  precise but assumes car is not moving. Momentum
  changes the timing so NOP time delays are used to
  slow down car.
• Some timing and turning issues can be exploited.
  For example, if system executes FWD 1 then FL45
  immediately without a NOP in between then left
  turn angle is about 70 to 90 degrees rather than
  45. FL90 varies from 80 to 110 degrees. This can
  shift error margin of overall course if
  necessary.

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Conclusion

• System is versatile and works great. New routes
  and timing adjustments can be easily entered in
  RAM in a few seconds compared to several minutes
  to recompile Verilog code.
• Error difficult to manage without feedback.
• Better car next time, perhaps?

QUESTIONS?