Architecture of Datapath-oriented Coarse-grain Logic and Routing for FPGAs

1
Architecture of Datapath-oriented Coarse-grain
Logic and Routing for FPGAs

• Andy Ye, Jonathan Rose, David Lewis
• Department of Electrical and Computer Engineering
  University of Toronto
• yeandy, jayar, lewis_at_eecg.utoronto.ca

2
Outline

• Motivation
• Datapath regularity
• An datapath-oriented FPGA
• Architecture
• CAD flow
• Experimental results
• Area efficiency
• Conclusion

3
Modern FPGAs

• Very large logic capacities
• Over 10 million equivalent logic gates
• Increasingly used to implement large and complex
  applications
• Central processing units
• Graphics accelerators
• Digital signal processors
• Packet switching networks

4
Datapath Circuits

• Large applications
• Contain a greater amount of datapath circuits
• Datapath circuits
• Consist of multiple identical logic structures
  called bit-slices
• Regularity
• Predictability

5
An Example
Full Adder
Full Adder
Full Adder
Full Adder
Carry In
Carry Out
6
An Example
7
Research Goal

• Design a new FPGA architecture
• Utilize datapath regularity
• Reduce the implementation area of datapath
  circuits on FPGAs
• Implement a full set of CAD tools for the new
  architecture
• Synthesis
• Packing
• Placement
• Routing

8
Key Architectural Features

• A bus-oriented logic block architecture
• A mixture of coarse-grain tracks and fine-grain
  routing tracks

9
Datapath FPGA Overview
Routing Channels
10
Logic Block Super-cluster
Cluster 4
Cluster 3
Cluster 2
Cluster 1
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Datapath FPGA Overview
Routing Channels
12
Coarse-grain Routing Tracks
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CAD Flow

• CAD flow for the datapath-oriented FPGA consists
  of
• Synthesis
• Packing
• Placement
• Routing
• Conventional CAD flow
• Minimize area and delay metrics
• Destroy datapath regularity

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Datapath-oriented CAD Flow

• Preserve datapath regularity (bit-sliced
  structures)
• Map the preserved regularity onto the
  datapath-oriented FPGA architecture
• Maximize the utilization of coarse-grain routing
  tracks
• Minimize the implementation area of datapath
  structures

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Datapath Representation

• Datapath circuits are represent by netlists of
  datapath components (VHDL or Verilog)
• Datapath component library
• Multiplexers
• Adders/subtracters
• Shifters
• Comparators
• Registers
• Each component consists of identical bit-slices

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Synthesis

• Enhanced module compaction algorithm
• Based on the Synopsys FPGA compiler
• Augmented with several datapath-oriented features
• Preserve datapath regularity by preserving
  bit-slice boundaries
• Achieve as good area results as the conventional
  synthesis tools

17
An Example Datapath Circuit
sel
cin
cout
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Synthesis
a0
b0
mux
sel
c0
d0
cin
s0
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Synthesis
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Packing

• Based on the T-VPACK packing algorithm
• Pack adjacent bit-slices into super-clusters
• Utilize carry connections in super-clusters to
  minimize the delay of carry chains

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An Example

• Four clusters per super-cluster
• Two BLEs per cluster
• Six inputs per cluster

BLE
BLE
BLE
BLE
BLE
BLE
BLE
BLE
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Packing Into Clusters
BLE
BLE
BLE
d0
cin
BLE
BLE
BLE
BLE
s0
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Packing Into Super-clusters
BLE
BLE
BLE
BLE
BLE
BLE
BLE
BLE
d0
d1
d2
d3
cin
BLE
BLE
BLE
BLE
BLE
BLE
BLE
BLE
s0
s1
s2
s3
cout
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Placement

• Based on the VPR placer
• Use simulated annealing algorithm
• For super-clusters containing datapath circuits
• Move super-clusters only
• For super-clusters containing non-datapath
  circuits
• - Move individual clusters

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Routing

• Based on the VPR router
• Use the path finder algorithm
• As much as possible
• Route buses through coarse-grain routing tracks
• Route individual signals through fine-grain
  routing tracks
• When necessary
• Use coarse-grain routing tracks for individual
  signals
• Use fine-grain routing tracks for buses

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Area Efficiency

• Benchmarks
• 15 datapath circuits from the Pico-java processor
• Architectural assumptions
• Four BLEs per cluster
• Four clusters per super-cluster
• Four coarse-grain tracks sharing configuration
  memory
• Logic track length of two
• Disjoint switch block topology
• Architectural variables
• Number of coarse-grain tracks

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Area Efficiency
normalizedcircuit area
circuit area in minimumtransistor area (x106)
100.0
1.60
95.0
1.50
90.0
1.40
0
0- 10
10- 20
20- 30
30- 40
40- 50
50- 60
60- 70
of coarse-grain tracks
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Logic Track Length Vs. Area

• Architectural assumptions
• Four clusters per super-cluster
• Four coarse-grain tracks share configuration
  memory
• 50 of tracks are coarse-grain tracks
• Disjoint switch block topology
• Architectural variables
• Number of BLEs per cluster
• Logic track length

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Logic Track Length Vs. Area
circuit area inminimum transistor area (x106)
N 2
N 4
2.20
N 8
2.00
N 10
1.80
track length
1.60
1
2
4
8
16
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Conclusion

• Proposed a datapath-oriented FPGA architecture
  and its CAD tools
• Best area is achieved when
• 40 - 50 of tracks are coarse-grain routing
  tracks
• Four BLEs per cluster
• Logic track length of two
• Best area is 9.6 smaller than conventional FPGAs