Sector Processor Simulation Status

1
Sector Processor Simulation Status

• Bobby Scurlock
• University of Florida
• February 2002

2
Outline

• Improvements to ORCA SP SW Model LUTs.
• Change over to ORCA-fied Verilog SP SW Model.
• Results from ME1/1a Strip Study
• Future Improvements to SP.

3
Changes to SP SW Since May 2001

• In ORCA Trigger Primitive improvement.
• ORCA SP SW Model will includes new cuts on Df and
  Dh to reduce background rates.
• In ORCA PT definition using 90 of efficiency
  curve maximum has been retuned.
• Change from Xilinx schematic based SP design to
  Verilog program complete.
• Verilog code translated to C SP to be
  integrated in to ORCA environment will replace
  current SP software model.
• Studies to be conducted on improving Pt
  resolution using bend angle.

4
Basic Design of SP Logic
BXA Allows SP to analyze track segments received
out of time. EU Test consistency of 2 track
segments to share track. TAU Links successfully
extrapolated segments. FSU Selects best 3
tracks, cancels redundant tracks. AU Assigns Pt
value and uncertainty.
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Extrapolation Unit

• h Road Finder
• Check if track segment is in allowed trigger
  region in h.
• Check if Dh and h bend angle are consistent with
  a track originating at the collision vertex.

• Quality Assignment Unit
• Assigns final quality of extrapolation by looking
  at output from h and f road finders and the track
  segment quality.

• f Road Finder
• Check if Df is consistent with f bend angle fb
  measured at each station.
• Check if Df in allowed range for each h window.

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Tuning Dh LUT
We use 6 bits for h in range 0.9-2.5. ? we have
0.025 h-unit binning.
Dh plots show best window to be one h-bin (0.025
h-units).
1 h-bin
Plots generated using single muon events for
Pt3GeV/c.
h2
h1
z
This takes advantage of h corrections in SR for
ME1/1
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Tuning Dfh LUTs
We can further restrict Df range by looking in
each of the 64 h bins in end-caps, and finding
the maximum allowable Dfh value. We do this
for Low Pt 3 and 5 GeV/c (Depends on EU) Med
Pt 15 GeV/c High Pt 25 GeV/c
Df41 cut
h
z
Df cut
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CSC Trigger Efficiency vs. PT
10
20
40
60
1.2 lt ? lt 2.4
Efficiency as of May
Current Efficiency
Trigger threshold defined at 90 efficiency
Efficiency unaffected by new cuts and improved
since May (with Improved trigger)
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CSC Single Muon Rate
Loose Track Criteria Tight Track Criteria
Trigger Rate (Hz)
105 104
Current Rate
Rate as of May
1 10
90
Ptcut (GeV/c)
Rate reduced by half
Weighted minimum bias sample used to estimate
rate for L 1034
Plots converge at Ptcut8 GeV/c. So, new cuts
only helpful in low Pt range.
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NEW Tuning Dfh, fb LUTs
We will use correlation between Df and fbend to
find allowed range for Df in a given h and fbend
bin This will also allow us to further untangle
low Pt from high Pt tracks.
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Current fb CSCs
These are just the CLCT Pattern Numbers.
These patterns are defined for both half and
di-strip track segments corresponding to high and
low momentum tracks
Patterns 1 and 2 are very similar. They do not
give enough bend information.
Strip
1
0
-1
-2
-3
2
3
CLCT Pattern Number
12
NEW Tuning Dfh, fb LUTs
Extrapolation Type ME1-ME2 fbend given by CSCs
Need more half strip fbend patterns from CSCs.
With the current Trigger design, we do not have
enough information to establish cuts or to
discriminate low from high Pt tracks.

• Placing fbend cutting on fbend -2
• Brings trigger efficiency down to 95
• Rate only reduces by 50 for Ptlt7

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Current Status of Verilog SP Model

• Sector Processor SW Modification Scheme

ORCA SP C Model
ORCA SP C Model
ORCA SP C Model
ORCA SP C Model
Verilog SW Model checked against ORCA SP Model
in perfect agreement
Model Change
Verilog HW Program
Verilog HW Program
Verilog HW Program
Verilog HW Program
Verilog C Traslation
Verilog C Traslation
Verilog C Traslation
Verilog C Traslation
t
t0
ORCA-fication Complete!
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New Development Scheme

• Post ORCA-fication

Verilog C Traslation
Verilog C Traslation
Verilog C Traslation
Verilog C Traslation
Model Change
Verification
Verilog HW Program
Verilog HW Program
Verilog HW Program
Verilog HW Program
t
t0
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Verilog SP Model
Sample of Verilog SP SW Model Translated to C
///include ltconio.hgt include ltmath.hgt include
ltstrstreamgt include "Trigger/L1CSCTrackFinder/int
erface/L1MuCSC_SPverilog.h" module
L1MuCSC_SPverilogSP ( input me1aQp, input
me1aEtap, input me1aPhip, input me1aAmp, input
me1aFRp, input me1bQp, input me1bEtap, input
me1bPhip, input me1bAmp, input me1bFRp, input
me1cQp, input me1cEtap, input me1cPhip, input
me1cAmp, input me1cFRp, input me1dQp, input
me1dEtap, input me1dPhip, input me1dAmp, input
me1dFRp, input me1eQp, input me1eEtap, input
me1ePhip, input me1eAmp, input me1eFRp, input
me1fQp, input me1fEtap, input me1fPhip, input
me1fAmp, input me1fFRp, input me2aQp, input
me2aEtap, input me2aPhip, input me2aAmp, input
me2bQp, input me2bEtap, input me2bPhip, input
me2bAmp, input me2cQp, input me2cEtap, input
me2cPhip, input me2cAmp,
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Verilog SP Model

• Currently, Implementation of Verilog SP Model is
  controlled with a switch in the .orcarc file.
• Set to become the default in ORCA 6
• The current switch is CSCTrackFinderverilog
  1
• Other Switches in the .orcarc file include
• Enable Low Quality Muons in the forward region
• CSCTrackFinderlowQualityFlag 3
• Enable Ganging of ME1/1a
• CSCTrackFinderORedME1A 1
• MuonEndcapORedME1A 1

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ORCA 6 ME1/1a Ored Strip Study

• Enabling Ganging of ME1/1a
• Generated 98 single muons with
• 50 lt Pt lt 100 and 2.0 lt h lt 2.4
• Full ME1/1a
• CSC TF reconstructs 56 tracks with Ptgt10GeV
• ME1/1a Ganged 3-Strips, No ghosts
• CSC TF reconstructs 27 tracks with Ptgt10GeV
• Loose ms to low Pt tracks
• ME1/1a Ganged 3-Strips, created ghosts
• CSC TF reconstructs 51 tracks with Ptgt10GeV
• Recovered ms
• Therefore, eghost 90

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Conclusions

• Whats been done in ORCA 6?
• Dh windows installed
• New Dfh cuts installed for ME1 and MB1
  Extrapolations
• Default Verilog Based SP SW Model controlled by
  switch
• Soon to come
• Use 7 bits for h to allow finer tuning in h
  windows.
• Install Dfh cuts for other Extrapolation types.
• Install Dfh, fb cuts using improved CLCT
  pattern numbers.
• Improve Pt resolution using parameterized fits in
  both h and fb windows long term.
• Include SP Bunch crossing analyzer in ORCA
  improve efficiency