A Comprehensive Platform for HardwareSoftware Codesign

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A Comprehensive Platform for Hardware-Software
Codesign
Andreas Koch Tech. Univ. Braunschweig Abteilung
Entwurf integrierter Schaltungen koch_at_eis.cs.tu-bs
.de
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Overview

• Common prototyping requirements
• Our approach
• Hardware Architecture
• Software Environment
• Summary

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Prototyping Requirements 1

• Prototyping of Systems
• Interaction of dependent
• Hardware
• Software
• Simulation often infeasible
• Models too complex
• Excessive run-times
• Audio/Video/Image processing

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Prototyping Requirements 2

• Too complex for breadboarding
• ASIC Emulation
• Large capacities (? 20Mgates)
• HW/SW coupling difficult
• Very expensive
• Wishlist
• Sufficient prototyping capacity
• Integrated solution
• Cost effective for smaller teams

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Proposed Solution

• Combines off-the-shelf components
• Economical
• 1-3 Mgates capacity
• Tight HW/SW coupling
• On-board CPU
• No interference from host CPU or OS
• Software support
• Complete tool chain
• Stand-alone OS

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ACEcard 1
PCI
PCI
i960
uSPARC-II
PLX
PLX
XC4085XL
XC4085XL
PMC
DRAM
XBAR
SRAM
SRAM
ACE2card
Host Computer

• Lavalogic ACEcard
• PCI expansion card

PCI
DRAM
UltraSPARC-II
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ACEcard 2

• Embedded Processor System
• 100 MHz microSPARC-IIep RISC
• 64 MB DRAM
• 1 MB Flash (firmware)
• Reconfigurable Processing Unit
• 2x XC6264 (ACE1)
• 2x XC4085XL (ACE2)
• 2x 256kx32b SRAM
• 2x 4kx36b FIFOs

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ACEcard 3

• Local RPU bus
• i960-like protocol
• Non-multiplexed, simpler than PCI
• Variable clock 0.5 - 33Mhz
• i960 ? PCI via PLX9080
• 32b wide, 33 Mhz
• Local PCI bus
• Host PCI bus
• Complete system on a board
• No interference by host

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ACEcard 4

• Already productive HW environment
• Old FPGA architecture
• Limited capacity
• Slow configuration speed (0.9s)
• No access from RPU to EPS
• Heterogeneous memory model
• Requires copy data to/from RPU SRAM

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ADM-XRC 1

• Alphadata Parallel Systems ADM-XRC
• PMC daughterboard
• Attaches to ACE PMC slot

Programmable I/O
Xilinx Virtex XCV1000
PLX 9080
i960
PCI
PMC
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ADM-XRC 2

• ZBT SSRAM instead of SRAM
• Modern FPGA
• 1 Mgates
• Fast configuration speed
• Partially reconfigurable
• Better access to PLX9080
• FPGA can master local PCI bus

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Combined Hardware Features

• Embedded RISC processor
• Isolated from host CPU
• Independent PCI bus
• Easy access from host workstation
• Modern FPGA architecture
• Large logic capacity
• Fast FPGA-local memories
• Homogeneous memory model

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Original Host-side Software

• ACE Device files for
• DRAM, SRAM
• Host and local PLX9080
• Programmable clock
• FPGA data and configuration
• Four virtual serial ports (VSP) to EPS
• ACE Basic tools for downloading
• EPS programs, RPU configurations
• ADM-XRC None (invisible to host!)

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Original EPS-side Software

• ACE Memory-mapped registers
• Host and local PLX9080s
• Four VSPs to host
• FPGA configuration, data and memories
• Programmable clocks
• ADM-XRC Memory-mapped registers
• PLX
• FPGA configuration and data
• Programmable clock

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Software Deficiencies

• No consistent API for HW access
• Configuration download protocols
• Clock programming
• IRQ handling
• Not even basic OS services on EPS
• Memory management (malloc, etc.)
• Math (sqrt, etc.)
• Signal handling
• No I/O beyond virtual serial ports

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RTEMS 1

• Real-Time Executive for Multiprocessor Systems
• Pre-emptive multi threaded RT-OS
• Lightweight
• No virtual memory management required
• Efficient direct hardware access
• Short IRQ latencies
• Flexible I/O driver model
• POSIX-compliant C library

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RTEMS 2

• Port RTEMS 4.0.0 to EPS
• SPARC V7 base port available
• Add ACE specifics
• RT clock
• MMU setup
• Cache control
• IRQ handling
• GNU tool chain to SPARC V8 target
• gcc, gas, gld, gdb
• Run conventional C code (but no I/O!)

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Host I/O Access

• Transparent access to host resources
• File system (including devices)
• Pipes
• Strategy
• RTEMS driver forwards I/O operations
• Asynchronous request via VSP
• Host-side I/O server
• Waits for I/O requests on VSP
• Reads parameter blocks from ACE DRAM
• Performs I/O using host OS
• Copies data back to ACE DRAM (DMA)

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Hardware Access

• Consistent API hides
• Resource-specific access protocols
• Reading/writing to hardware registers
• Functions
• Fast configuration loading
• Can handle compressed bitstreams
• Determine FPGA memory ranges
• Synchronization with RTEMS threads
• IRQ handling
• Clock programming

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Software Architecture
User Application
RTEMS API
POSIX API
Host Filesystem
ACE API
Host I/O Server
RTEMS Kernel
ACE I/O Driver
Lavalogic Drivers
VSP
Mapped DRAM
VSP
DRAM
i960
PCI
PCI
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Summary

• Flexible Platform for HW/SW Codesign
• Dedicated CPU independent from host
• Transparent access to host resources
• Large hardware prototyping capacity
• Easy to use
• Complete SW environment
• Capable yet lightweight OS
• Complete tool flow
• Cost-effective design