9'3RULES FOR BIPOLAR TRANSISTOR MATCHING

1
9.3RULES FOR BIPOLAR TRANSISTOR MATCHING
Minimal matching Typical three-sigma offset
voltages of 1mV or collector current
mismatches of 4.This is suitable for
constructing input stages of op-amps and
comparators that must achieve three-sigma offsets
of 3 to 5 mV without trim. It is also
suitable for use in current mirrors for biasing
non-critical circuitry.
2
Moderate matching Typical three-sigma offset
voltages of 0.25mV or collector current
mismatches of --1. This level is suitable for
use in 1 bandgap references and in op-amps
and comparators that must achieve 1 to 2mV
without trim. Since lateral transistors have
difficulty maintaining this degree of matching,
most untrimmed, moderately matched circuits use
vertical NPN transistors instead.
3
Precise matching Typical three-sigma offset
voltages of 0.1mV or collector current
mismatches of 0.5 . This level of matching
usually requires trimming or the addition of
precisely matched degeneration resistors. Proper
layout is still important because degeneration
and trimming cannot entirely eliminate the
effects of thermal gradients or package shifts.
Lateral transistors cant obtain this degree of
matching unless they are heavily degenerated and
the circuitry incorporates some means of base
current cancellation. Circuits requiring precise
matching usually employ heavily degenerated
vertical NPN transistors.
4
Rules for Matching NPN Transistors
1. Use identical emitter geometries.
2. The emitter diameter should equal 2 to 10
times the minimum allowed diameter. For example,
a process having a minimum contact width of 2 um
and a minimum overlap of I um has a minimum
emitter diameter of 4 um. Matched emitters in
this process should have diameters of 8 to 40 um.
5
3. Maximize the emitter area-to-periphery ratio.
4. Place matched transistors in close proximity.
5. Keep the layout of matched transistors as
compact as possible.
6. Construct ratioed pairs and quads using even
integer ratios between 41 and 161. -- between
41 and 161 for ratioed pairs -- between 41
14 and 811 8 for ratioed quads.
6
7. Place matched transistors far away from power
devices. Minimally matched transistors ---- 250
um away from devices dissipating 250mW or more
should not reside adjacent to device
dissipating more than 50mW
8. Place matched transistors in low-stress
areas. near center of Die preferred near
middle of edge acceptable
9. Place moderately or precisely matched
transistors on axes of symmetry of the die. S1
axis // to Symmetry Axis of Die
11. Place emitters far enough apart to avoid
interactions. spacing between the matched
emitters should exceed the minimum spacing by 2
to 3 um.
7
12. Increase the base overlap of moderately or
precisely matched emitters. base region of a
moderately or precisely matched transistor should
overlap its emitter by 1 to 2um more than
minimum.
13. Operate matched transistors on the flat
portion of the beta curve.
14. The contact geometry should match the emitter
geometry.
15. Consider using emitter degeneration. Minimall
y matched -- not Moderately maybe if large
Temp gradient 50mV Precisely matched
transistors are often degenerated 100mV If used
in matching different sized Transistors,
then Use Emitter degenrate Resistors 200mV for
Minimal Match 500mV for moderate
match Example) Match the NPN with ratio 1.641