Test Chip Measurement Update

1
Test Chip MeasurementUpdate

• Andy Liu

2
Test Chip

• 12X9 transistor array
• NMOS and PMOS
• Different sizes
• Three copies
• 4 ring oscillators
• min. size
• bigger size
• ELT
• Current mode
• 5 shift Registers
• Std
• ELT
• Various resistors
• ELT majority voting
• New scheme
• 6 individual gates
• std ELT Not
• std ELT Nand
• std ELT Nor

4 Ring oscillators
PLL parts
12 X 8 Transistor Array
5 Shift registers
6 Individual Gates
3
T-Schematics
12 columns, 4 different width and length 3
columns with the same width and length
Vdd2
Vdd1
Vdd12
NMOS 4 rows
Vgg1
Vss1
PMOS 4 rows
Vss2
Vgg8
4
T-Measurements

• Measure Ids Vgs curve (Vds is fixed at 0 V, 0.1
  V, and 2.5 V) at several dose levels. Calculate
  Vth, Transconductance (gm), and subthreshold
  slope.
• Measure periodically, e.g., every one minute, one
  transistor at one time and leave all others
  transistor terminals floating. Bias all
  transistors when not measured.

Log10(Ids)
PMOS
NMOS
Log10(Ids)
Vth
Vgs
Vds2.5V
Vds0
Vds0.1V
Vds0.1V
Vds0
Vds2.5V
Vgs
Vth
5
T-Measurement Devices

• Instruments needed.
• 2 programmable voltage sources (Vgs and Vds)
• 1 current meter (Ids)
• switch array
• Programmable Voltage sources (Vgs and Vds)
• Range 0 2.5V
• Agilent E3631A, 2 independent outputs, resolution
  1mV
• Current (Ids)
• 1 uA 300 uA when on, 15 pA 450 pA when off
• 1200, Keithley 6845 5 ½ digits, 8 ranges in
  20fA 20 mA

6
T-Bias
PV10V
GND
Bias all transistors in the same way when not
measured
D
S
PV22.5 V
PV2 2.5 V
S
D
NMOS
PMOS
GND
PV10V
2.5V
Bias the transistor measured and leave all
other terminals floating
PV1
S
D
PV1
PV2
D
S
PMOS
PV1
NMOS
GND
7
T-Switch Array Configuration
8
T-Switch Configuration (when measured)
Vss1
Vdd1
Vgg1
2.5V
Vss2
Vdd2
Vgg2
Vdd3
Vss3
Vgg3
Vdd4
Vgg4
Vdd5
Vss4
PV1
PV2
Vdd6
Vgg5
Ids
Vdd7
Vss5
Vgg6
Vdd8
Vgg7
Vdd9
Vss6
Vdd10
Vgg8
Vdd11
Vss7
Vdd12
GND
Vss8
9
T-Switch Configuration (when not measured)
Vss1
Vdd1
Vgg1
2.5V
Vss2
Vdd2
Vgg2
Vdd3
Vss3
Vgg3
Vdd4
Vdd5
PV2 2.5V
Vgg4
PV1
Vss4
Vdd6
Vgg5
Ids
Vdd7
Vss5
Vgg6
Vdd8
Vdd9
Vgg7
Vss6
Vdd10
Vgg8
Vdd11
Vss7
Vdd12
GND
Vss8
10
Gates-Schematics
VDD1
In1
Out1
STD NAND
In2
VDD1
ELT NAND
Out2
VDD1
STD NOR
Out3
VDD1
ELT NOR
Out4
VDD1
Out5
STD INV
VDD1
Out6
ELT INV
GND
11
Gates-Transfer Function

• Power current online monitored by using Keithley
  2700
• Measure the DC transfer curve Vout(Vin)
• 1 programmable voltage source
• 1 voltage meter
• 1 switch array

Vout
Vin
0
12
Gate-Switch Config. (measured)
Vo1
Vo2
PV1
Vo3
Vin1
PV2
Vin2
Vo4
DMM
Vo5
Vo6
Switch Config. (not measured)
Vo1
Vo2
PV1
Vo3
Vin1
PV2
Vin2
Vo4
DMM
Vo5
Vo6
13
TG-SW Config. (measured)
Vdd1
Vgg1
Vdd2
Vgg2
Vdd3
Vss1
Vgg3
Vdd4
Vgg4
Vdd5
2.5V
Vss2
PV1
PV2
Vdd6
Vgg5
Ids
Vdd7
Vss3
Vgg6
Vdd8
Vgg7
Vdd9
Vss4
Vdd10
Vgg8
Vdd11
Vss5
Vin2
Vdd12
Vo1
Vin1
Vss6
Vo2
Vo3
Vss7
Vo4
DMM
GND
Vo5
Vss8
Vo6
14
TG-SW Config. (not measured)
Vdd1
Vgg1
Vdd2
Vgg2
Vdd3
Vss1
Vgg3
Vdd4
Vdd5
PV2 2.5V
Vgg4
2.5V
Vss2
Vdd6
Vgg5
Ids
Vdd7
Vss3
PV1 0
Vgg6
Vdd8
Vdd9
Vgg7
Vss4
Vdd10
Vgg8
Vdd11
Vss5
Vin2
Vdd12
Vo1
Vin1
Vss6
Vo2
Vo3
Vss7
Vo4
DMM
GND
Vo5
Vss8
Vo6
15
RO-Schematics
VDD1
Std small
Enable
Out1
GND
RO_Out1
VDD2
RO_Out2
Std big
Out2
RO_Out3
Counter
GND
VDD3
BNC
Out3
ELT
RO_Out5
GND
VDD4
125 uA Ib
Out4
Diff Mode
125 uA Iref
Out5
PowerOn
GND
16
RO-Ring Oscillators

• Power current monitoring online using Keithley
  2700
• Frequency online monitoring by using
• Frequency counter
• High speed switch to scan

17
RO-Frequency Counter
http//www.usbgear.com/USBG-232MINI.html
18
Switching Board Function
Vdd1
Vgg1
Vdd2
Vgg2
Vdd3
Vss1
Vgg3
Vdd4
Vdd5
PV2 2.5V
Vgg4
2.5V
Vss2
Vdd6
Vgg5
Ids
Vdd7
Vss3
Vgg6
Vdd8
Vdd9
Vgg7
Vss4
Vdd10
Vgg8
Vdd11
Vss5
Vin2
Vdd12
Vo1
Vin1
Vss6
Vo2
RO_Out1
Vo3
Counter
Vss7
Vo4
RO_Out2
DMM
GND
Vo5
RO_Out3
BNC
Vss8
Vo6
RO_Out5
19
Switching Board Function

• Low speed switches
• One 113
• One 19
• One 16
• One 28
• High Speed switches
• One 14
• Total switches 96 for two carrier boards
• Plus a switch for each VDD to prevent circuit
  short (additional 18 switches)

20
Switching Board Block Diagram
Carrier Board 1
PV2
Transistor Array
2.5V
PV1
Gate Array
Ring Oscillator
DMM
FPGA Board
Switch Board
114
Carrier Board 1
Transistor Array
Frequency Counter
Ring Oscillator
Gate Array
21
Switching Board-Ground
Switch Board
Vdd
PS1
Carrier Board 1
RO1
gnd
RO2
Vdd
PS2
RO3
Carrier Board 2
RO1
RO2
Freq. Counter
RO3
BNC
22
Switching Board-Dry Reed Relays

• Low speed relays
• Coto 9117, 0.4 x 0.15, 5.94/each (min. 100)
• Coto 9007, 0.76 x 0.2, 0.79/each (min. 100)
• 100 relays 15.2 in2
• High speed relays
• Coto 9802, 50 ohm, up to 6GHz, 4.75/each (min.
  100), 0.51 x 0.2, surface mounting

23
Shift Registers
Vdd
SR-std
out
Vdd

• Pins total 22
• Vdd 5
• GND 3
• Output 6
• Input 8
• Data 4
• Clk 4

clk
out
SR-ELT
data
gnd
Vdd
clk
out
SR-Maj Vot
err
data
Vdd
clk
SR-Res
out
data
gnd
Vdd
clk
out
SR-set
data
gnd
24
Shift Registers - Continue

• SR1 (std), SR2 (ELT), SR3 (ELT majority
  voting), SR4 (new) all stages are the same.
  Shift in/Shift out at a fixed speed, e.g.,
  100Mb/s and compare
• SR5 (resistor) each stage has a different
  resistor. Shift in at 100 Mb/s, wait for 1
  second, shift out at 100 Mb/s. If SEU happens not
  during the transmission process, we can determine
  where the SEU happens

25
Shift Registers

• Test bit error rate by using an FPGA. It is easy
  for the data rate up to 200 Mb/s.
• Monitor power supply current by using Keitheley
  2700.

DUT Shift registers
Error Counter
Pattern Generator
Comparator
Shift registers
clock
26
Shift Registers
Carrier Board 1
SR1
SR2
SR3
8
SR4
6
FPGA Board
SR5
8
Carrier Board 2
SR1
SR2
6
SR3
SR4
SR5
27
PLL
2.5V CMOS input/output Around 155 MHz
Data
PFD
Up
Down
Clk
VCP 1.5V VCN 0.8V Bias 0.7V Output 2.3GHZ,
DC2.3V AC70mV 50 Ohm
VCP
VCO
Out
VCN
Out-
BIAS
Clk
DIV16
Out
Input 2.6 GHz sine wave, DC1.5V AC
0.5V Output 160 MHz square wave, 2.5V
CMOS Vbias 0.8V
Clk-
Vbias
28
PLL-PFD
Vdd
Data
Up
PDF
Signal Generator
Oscilloscope
50
Clk
1k
Down
50
BNC
50
BNC
gnd
Probe Test Points
2.5V CMOS input/output Around 155 MHz
29
PLL-VCO
Vdd
SMA
1.5V VCP
Out
VCO
Oscilloscope
0.8V VCN
0.7V Bias
Out-
50
SMA
gnd
Probe Test Points
VCP 1.5V VCN 0.8V Bias 0.7V Output 2.3GHZ,
DC2.3V AC70mV 50 Ohm
30
PLL-DIV16
Vbias 0.8V
Vdd
SMA
Clk
DIV16
Signal Generator
BNC
Oscilloscope
50
Clk-
1k
Out
50
50
SMA
gnd
Probe Test Points
Input 2.6 GHz sine wave, DC1.5V AC
0.5V Output 160 MHz square wave, 2.5V CMOS
31
PLL-Power Supply
2.5V
Power Supply number 2.5V 3 1.5V 1 0.8V
2 0.7V 1 Total 7
PFD
2.5V
VCP
VCO
VCN
BIAS
2.5V
DIV16
Vbias
32
Power Supply

• Gates 2.5V 6
• Ring Oscillators 2.5V monitored 4
• Assistant input control signal input, not
  monitored
• 2.5V 1
• -125 uA 1
• 125 uA 1
• Shift Registers 2.5V 5
• PLL 2.5V 3
• Assistant input not monitored, get from 2.5V
  using resistors
• 1.5V 1
• 0.8V 2
• 0.7 V 1

33
Power Supply Schematics
Voltage Regulator
Current Sensor
Voltage Regulator
6 Adjustable voltage output with shared ground
Current Sensor
AC-DC converter
Voltage Regulator
Current Sensor
Current measurement
34
Power Supply-Current Sensor
35
System-Measurements
36
System-Block Diagram
RS232
Freq. Counter
Flux Counter
GPIB
Prog. V. Source
GPIB
Picoammeter
Test chip Carrier Board 1
PC
Switch Board
PCMCIA Digital IO Card
Test Chip Carrier Board 2
FPGA Board
TTL??LVDS
GOL Board 1
TLK Rx
TTL?LVDS
GOL Board 2
TTL?LVDS
TLK Rx
Power Supply Board
GPIB
DMM
Control Room 37 m away
In the beam
1 m away from the beam
37
System-Block Diagram
RS232
Freq. Counter
GPIB
Prog. V. Source
GPIB
Picoammeter
Test chip Carrier Board 1
PC
Switch Board
Flux
Test Chip Carrier Board 2
USB DIO Card
FPGA Board
GOL Board 1
TLK Rx
TTL?LVDS
GOL Board 2
TTL?LVDS
TLK Rx
Power Supply Board
GPIB
DMM
Control Room 37 m away
In the beam
2 m away from the beam
38
System-Block Diagram
RS232
Freq. Counter
GPIB
Prog. V. Source
GPIB
Picoammeter
Test chip Carrier Board 1
PC
Switch Board
Flux
Test Chip Carrier Board 2
FPGA Board
USB
GOL Board 1
TLK Rx
TTL?LVDS
GOL Board 2
TTL?LVDS
TLK Rx
Power Supply Board
GPIB
DMM
Control Room 37 m away
In the beam
2 m away from the beam
39
System-Instrument Interface
Freq. Counter
RS232 cable
USB? RS232
USB Cable
PC
USB? GPIB
GPIB Cable
Prog. V. Source
GPIB Cable
Daisy Chain
Picoammeter
GPIB Cable
DMM
Control Room 37 m away
In the beam
2 m away from the beam
40
DIO Card
41
System-Schedule
10/1/05
System design 1 month
11/1/05
Schematic capture 1 month
12/1/05
PCB layout 1 month
1/15/05
Board assembly 3 wk
FPGA code 1.5 month
Labview code 1 month
2/15/06
Debug 3 wk
3/1/06
Lab Test 1 month
3/31/06
Field Test