FPGA Stuff State Machines and VGA Timing project

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FPGA StuffState Machines and VGA Timing project

• Anselmo Lastra

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Outline

• Describe types of state machine
• Try to explain what synthesizer is doing
• Two types of timing generator designs

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Example State Machine
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Binary Encoded

• module binary (CLOCK, RESET, A, B, C, D, E,
  SINGLE, MULTI, CONTIG)
• input CLOCK, RESET input A, B, C, D, E
• output SINGLE, MULTI, CONTIG
• reg SINGLE, MULTI, CONTIG
• // Declare the symbolic names for states
• parameter 20
•     S1 3'b001,
•     S2 3'b010,
•     S3 3'b011,
•     S4 3'b100,
•     S5 3'b101,
•     S6 3'b110,
•     S7 3'b111
• // Declare current state and next state variables
  
• reg 20 CS
• reg 20 NS
• (continues)

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Binary Encoded (2) Reset

• always _at_ (posedge CLOCK
• or posedge RESET)
• begin
• if (RESET 1b1)
• CS S1
• else
• CS NS
• end
• (continues)

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Binary Encoded (3)

•     always _at_ (CS or A or B or C or D or D or E)
•     begin
•     case (CS)
•             S1
•             begin
•               MULTI 1'b0  CONTIG 1'b0
  SINGLE 1'b0
•             if (A B C)
•               NS S2
•             else if (A B C)
•               NS S4
•             else
•               NS S1
•             end
•             S2
•             begin
•               MULTI 1'b1 CONTIG 1'b0 SINGLE
  1'b0
•             if (!D)
•                 NS S3
•             else

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One-Hot Encoding (1)

• // Declare the symbolic names for states
• parameter 60
• S1 7'b0000001,
• S2 7'b0000010,
• S3 7'b0000100,
• S4 7'b0001000,
• S5 7'b0010000,
• S6 7'b0100000,
• S7 7'b1000000
• // Declare current state and next state variables
• reg 20 CS
• reg 20 NS

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Body Looks the Same

• always _at_ (CS or A or B or C or D or D or E)
• begin
• case (CS)
• S1
• begin
• MULTI 1b0
• CONTIG 1b0
• SINGLE 1b0
• if (A B C)
• NS S2
• else if (A B C)
• NS S4
• else
• NS S1
• end

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One Hot Preferred

• Docs say one hot better for larger state machines
  on xilinx
• Many FFs
• Narrow combinational logic

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Synthesizer Finds SMs

• Re-encodes
• Choose styles in preferences dialog box
• Reports finding and result
• Next page

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Synthesizer Output

• Found finite state machine ltFSM_0gt for signal
  ltstategt.
• --------------------------------------------------
  ----------
• States 6
• Transitions 10
• Inputs 2
• Outputs 6
• Reset type asynchronous
• Encoding automatic
• State register d flip-flops
• --------------------------------------------------
  ---------

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Re-encodes registers

• Code
• reg 20 inst
• Synthesizer Output
• Using one-hot encoding for signal ltinstgt.
• Found 8-bit register for signal ltinstgt.

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Tip from Xilinx Docs

• Manual showed style to eliminate a register to
  hold output
• Example next

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Reg for Output

• module fsm (clk, reset, x1, outp)
• input clk, reset, x1
• output outp
• reg outp
• reg 10 state
• parameter s1 2'b00
• parameter s2 2'b01
• parameter s3 2'b10
• parameter s4 2'b11
• (continues)

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Reg for Output

• always_at_(posedge clk or posedge reset)
• begin
• if (reset)
• begin
• state s1 outp 1'b1
• end
• else
• begin
• case (state)
• s1 begin
• if (x11'b1) state s2
• else state s3
• outp 1'b1
• end
• s2 begin
• state s4 outp 1'b1
• end

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Eliminate Output Reg

• Split Machine

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Code State Machine Part

• always _at_(posedge clk or posedge reset)
• begin
• if (reset)
• state s1
• else
• begin
• case (state)
• s1 if (x11'b1) state s2
• else state s3
• s2 state s4
• s3 state s4
• s4 state s1
• endcase
• end
• end

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Code Output Part

• always _at_(state)
• begin
• case (state)
• s1 outp 1'b1
• s2 outp 1'b1
• s3 outp 1'b0
• s4 outp 1'b0
• endcase
• end

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VGA Timing Generators

• Got two kinds
• Counters and combinational logic
• State machines
• Latter more software-like
• Seem more expensive

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SMs vs Combinational

• Number of Slices
• 91 out of 1200 7
• Number of Slice Flip Flops
• 72 out of 2400 3
• Number of 4 input LUTs
• 171 out of 2400 7
• Number of Slices
• 96 out of 1200 8
• Number of Slice Flip Flops
• 83 out of 2400 3
• Number of 4 input LUTs
• 135 out of 2400 5

• Number of Slices
• 25 out of 1200 2
• Number of Slice Flip Flops 29 out
  of 2400 1
• Number of 4 input LUTs 44 out
  of 2400 1
• Number of Slices
• 38 out of 1200 3
• Number of Slice Flip Flops 29 out
  of 2400 1
• Number of 4 input LUTs 70 out
  of 2400 2

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References

• Xilinx synthesis and simulation manual
• http//toolbox.xilinx.com/docsan/xilinx5/pdf/docs/
  sim/sim.pdf
• XST Manual
• http//toolbox.xilinx.com/docsan/xilinx5/pdf/docs/
  xst/xst.pdf