Design of PowerOptimal Buffers Tunable to Process Variability

1
Design of Power-Optimal Buffers Tunable to
Process Variability

• M. Mani, C. Caramanis, K. He and M. Orshansky
• University of Texas at Austin

2
Design-Time and Post-Silicon Tuning Based on
Affine Policies

• Developed co-optimization strategy for
  design-time and post-silicon yield improvement
• Design-time gate sizing
• Post-silicon tuning uses adaptive body biasing
  (ABB)
• Output of adjustable optimization is a set of
  first-stage decisions and a policy
• Policies limited to affine functions of the
  uncertain variables (Leff and Vth)

3
Adjustable Power-Efficient Buffers on
Timing-Critical Paths

• Multiple target applications for tapered buffers
• Embedded SRAM Both timing paths and power are
  dominated by buffer chains driving large wordline
  capacitances
• I/O circuits Drive large off-chip capacitances
• Clock trees Ensure that skew constraints are
  satisfied
• Global interconnect Exacerbating wire delays
  imply more buffers per unit length
• Growth of variability and leakage espouse
  low-power adaptive buffer design techniques
• Design-time techniques lack ability to react to
  actual conditions on chip and impose fixed
  overhead
• Use an adaptive strategy to reduce average total
  energy consumption in large buffers
• Pre-design redundant implementations and select
  after manufacture depending on uncertainty

4
Expanding Flexibility of Tuning Finite
Adjustable Optimization

• In general, optimization with recourse under
  uncertainty follows
• General adjustable problems with arbitrary
  dependence of variables on uncertain parameters
  are NP-hard
• For affine functions of the uncertain variables,
  we use fast interior point methods
• Problem affine formulations assume continuous
  adaptability
• Often only a small finite number of alternatives
  available
• Only 2 or 3 threshold voltages, a small number of
  cell drive strengths
• Second stage decisions are discrete, and chosen
  from a finite set of pre-determined contingency
  plans
• Choice depends on the realization of the
  uncertainty
• Earlier developed affine methods are not suitable
• Will solve the problem as a finite adaptable
  optimization problem under uncertainty

First stage decisions ? Observation of uncertain
variables ? Tune decision variables
5
Buffer Design and Characterization

• Design tuning based on buffer stages with
  different drive strengths
• Implemented using a tri-state like buffer
  configuration
• Both branches enabled for high-speed, extra
  branch turned off for low-power operation
• Delay of buffer modeled as a posynomial function
  of transistor widths
• Leakage and dynamic power have linear dependence

6
Finite Adaptable Buffer Design Strategy

• A two-stage problem under uncertainty but with
  finite adaptability
• First stage size buffers
• Second stage determine policy for turning on
  branch
• Minimize average power with satisfactory
  timing-yield
• Strategy solving above is equivalent to finding
  a partition of uncertainty set
• - partitions of uncertainty set, - first
  stage decision, - second stage decisions
• A second-stage decision corresponds to a
  partition

7
Formulating the Delay Constraints

• Consider variability in channel length
• Two possible partitions with as the truncation
  point
• Two different buffer configurations
• Select branch 1 with probability a1 branch 1 2
  with probability a2
• denotes the delay through the buffer
  configuration
• Delay is monotonic in the process parameters

8
Formulating the Objective Function

• The objective function is the total power of the
  configuration
• Dynamic power of a buffer computed as the sum of
  the dynamic powers of the individual components
• Adopt exponential model for leakage power
• Expected value of leakage power of buffer
  configuration
• where is the cdf of and
  is the cdf of

9
Adaptable Buffer Design Problem Solution

• Can re-write the problem as
• where , and are cdf of variables
• For each truncation point, we solve a geometric
  program
• Find optimal truncation point by a linear sweep
• This describes the optimal policy
• Similar strategy for handling variability in both
  L andVth
• Seeks partitioning of 2-D uncertainty set
• Use body bias as additional tuning variable to
  control area overhead

10
Partitioning Strategy Matters

• There exists an optimal partition for which the
  power is minimized
• Depends on the yield constraint
• Adaptive scheme produces a savings of 18 in
  total power

11
Buffer Design Example

• Designed buffer using optimization flow to obtain
  sizes and optimal partition
• SPICE simulation performed using 65nm technology
• Optimal Partition - Proportion of low-power
  buffer use is 0.78 and high-speed buffer use is
  0.22
• Total power savings compared to basic
  non-adaptable buffer 18.5
• Area overhead due to control transistors 14.6

12
Monte Carlo Simulation Results

• Significant spread in power and delay
• High-speed buffer used when low-power buffer does
  not meet timing

13
Conclusions

• A design strategy for finite adaptability is
  being developed
• Expands application domain compared to affine
  policies
• Discrete second stage adaptability potentially
  reduces implementation cost
• Partition of uncertainty set that dictates buffer
  switching policy is crucial to enabling power
  savings in adaptive setting
• Experiments indicate that up to 18 savings in
  total power and 17 savings in leakage are
  possible at acceptable area overhead
• Multiple target applications where adaptive
  buffer design can make a significant impact