Towards the limits of conventionnal MOSFETs

1
Towards the limits ofconventionnal MOSFETs
G. BERTRAND1, S. DELEONIBUS1, B PREVITALI1,G.
GUEGAN1, X. JEHL2, M. SANQUER2, F. BALESTRA3
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OUTLINE

• CMOS challenges
• Device fabrication
• Limits in terms of
• Short Channel effects
• Performances
• Transport
• Charge from CMOS to SET-MOS
• Conclusion

3
CMOS challenges
Possibilities of Conventional MOSFET?
4
Device fabrication

• Conventional MOSFET architecture- 1.2nm SiO2
  gate oxide
• - In situ doped polysilicon Gate
• - Channel non intentionnaly adjusted
• but Super Halo SH (only BF2 halos)
• or Non super Halo NSH (B II BF2 halos)
• - As extensions
• - 30nm nitride spacers
• - As HDD Source and drain
• - RTP spike anneal 1050C
• Gate length down to
  16nm

5
Limits short channel effects (SCE)
Electrical characteristics
V
1.5V
-3
10
d
V
50mV
d
-5
10
Lot 6893 P18B

• Field Effect transistor down to Lg16nm

Channel B 5keV
(A)
14
-2
LDD 1.5 10
cm
-7
10
D
I
13
-2
Halo 3.10
cm
tilt 22
L
29nm
g
-9
10
L
16nm
g
-11
10
-0,5
0
0,5
1
1,5
W10µm
V
(V)
G
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Limits short channel effects (2)

• Below 40nm, SCE not efficiently controlled
  whatever transistor architecture
• spacer length (30 to 40nm)
• halo dose (1-4.1013cm-2)
• LDD dose (0.8-2.1014cm-2)

Large punchtrough current below 40nm
Need for - Thinner gate oxide -
Improvement of halo efficiency
7
Limits SCE (3) Halos efficiency
Large B diffusion (TEDF)
Halos BF2 15-25keV
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Limits Ion/Ioff
High Rsd Low IonOptimum SCE Ioff control
Medium Rsd High IoffOptimum Ion

• Despite large Rsd (1200 ?.µm), Ion up to 900
  µA/µm
• Optimum Rsd / SCE trade-off hard to perform
  with such conventionnal architecture and
  technique

9
Limits transport (1)

• No velocity overshoot
• Quasi ballistic transport r with T
  but r0.5-0.6 whatever Lg lt 100nm

10
Limits transport (2)

• Impact at room temperature

Low field mobility degradation due to halo
overlapmostly in the case of efficient SCE
control
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Limits from CMOS to SET-MOS (1)

• Lg CMOS SET

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Limits from CMOS to SET-MOS (2)
gt 50 oscillations _at_1.7K (0.5 to 1.4V)
- Periodicity Related to Channel Geometry
// F. Buf et al results IEDM 2001on non
overlap Gate/Extension structure
Importance of Rsd in Coulomboscillation
observation
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Limits from CMOS to SET-MOS (3)

• Observable oscillations from 20K up to 75K
• à minimal gate length
• à high charging energy
• Aperiodic oscillations
• Large W (10µm)
• Enable SET- MOS
• operating temperature
• closer to room temperature if W is
  reduced

14
Conclusions

• Realization of conventional ultimate nMOSFET
• à functional devices physical gate length
  down to 16nm
• à electrical characteristics with good
  performance
• Limits With conventional As extension BF2
  halos architecture - difficult to control
  SCE below 40nm - limits low field mobility
  and non stationary transport
• Bulk à Need for thinner gate oxide (SCE
  control) à Need for ultra steep halo
  profile (improved annealing process, B or In
  halo dopant instead of BF2, epitaxial SiCx
  diffusion barrierVLSI 02)
• Alternatives low doped FDSOI, DGMOS.
• From CMOS to SET-MOS
• - Conventional MOSFET could operate as SET at
  temperature below 4.2K
• - Promising results have been shown for 77K SET
  operation