COE 341: Data

1
COE 341 Data Computer Communications
(T081)Dr. Marwan Abu-Amara

• Chapter 6
• Digital Data Communications Techniques

2
Contents

• Asynchronous and Synchronous Transmission
• Types of Errors
• Error Detection
• Parity Check
• Cyclic Redundancy Check (CRC)

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Asynchronous and Synchronous Transmission

• To communicate meaningful data serially between
  TX and RX, signal timing should be the same at
  both
• Timing considerations include
• Rate
• Duration
• Spacing
• Need to synchronize RX to TX
• Two ways to achieve this
• Asynchronous Transmission
• Synchronous Transmission

• RX needs to sample the received
• data at mid-points
• So it needs to establish
• - Bit arrival time
• - Bit duration

4
Need for RX and TX Synchronization

• Clock drift (example)
• If the receiver clock drifts by 1 every sample
  time,
• For Tb 1 msec, total drift after 50 bit
  intervals 50 X 0.01 0.5 msec
• i.e. instead of sampling at the middle, the
  receiver will sample bit 50 at the edge of the
  bit
• RX and TX clocks are out-of-synch ? Communication
  Error!
• In general, of correctly sampled bits 0.5
  Tb/(n/100)Tb 50/n,
• where n is the timing error between TX and RX
• Two approaches for correct reception
• Send only a few bits (e.g. a character) at a time
  (that RX can
• sample correctly before losing sync) ?
  Asynchronous Transmission
• Keep receiver clock synchronized with the
  transmitter clock ? Synchronous
  Transmission

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Asynchronous Transmission Character-Level
Synchronization

• Avoids the timing problem by NOT sending long,
  uninterrupted streams of bits.
• So data is transmitted one character at a time
• Has a distinct start bit
• Consists of only 5 to 8 bits (so drift will not
  be a serious problem)
• Has a distinct stop bit
• Character is delimited (at start end) by known
  signal elements start bit stop element
• Sync needs to be maintained only for the duration
  of a character
• The receiver has a new opportunity to
  resynchronize at the beginning of next character
• ? Timing errors do not accumulate from character
  to character

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Asynchronous Transmission
(Min)
Binary 1
Binary 1
RX waits for a character following the end of the
previous character

• The stop element confirms end of character ?
  otherwise Framing Error
• Stop elements continue (idling)
• until next character

RX knows how many bits To expect in a
character, and keeps counting them following
the start bit
Parity bit Even or Odd parity?
S1 receiver in idling state S2 receive in
receiving state
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Asynchronous Transmission

• Framing error
• Erroneous detection of end/start of a character
• Can be caused by
• Noise (1 is the idling stop bit)
• 1 1 1 1 0 1 1 1 1 1
• Incorrect timing of bit sampling due to drift of
  RX clock affects bit count

Erroneous Start bit due to noise
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Asynchronous Transmission

• Errors due to lack of sync for an 8-bit system
• Let data rate baud rate 10 kbps
• Bit interval 1/10k 100 ms
• Assume RXs clock is faster than TX by 6
  (i.e. RX thinks the bit interval
  is 94 ms)
• RX checks mid-bit data at 47 ms and then at 94 ms
  intervals
• Bit 8 is wrongly sampled within bit 7 (bit 7 read
  twice!)
• Possibility of a framing error at the end

893
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Asynchronous Transmission Efficiency

• Uses 1 start bit 2 stop bits (i.e. 3 non-data
  bits)
• with 8-bit characters and no parity
• ? Efficiency 8/(83) 72
• ? Overhead 3/(83) 28

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Asynchronous Transmission Pros Cons

• Advantages
• Simple
• Cheap
• Good for data with large gaps (keyboard)
• Cons
• Overhead of 2 or 3 bits per character (20)
• Timing errors accumulate for large character sizes

11
Synchronous Transmission Bit-Level
Synchronization

• Allows transmission of large blocks of data
  (frames)
• TX and RX Clocks must be synchronized to prevent
  timing drift
• Ways to achieve bit-level sync
• Use a separate clock line between TX and RX
• Good over short distances
• Subject to transmission impairments over long
  distances
• Embed clock signal in data
• e.g. Manchester or Differential Manchester
  encoding
• Or carrier frequency for analog signals

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Synchronous Frame Format

• Typical Frame Structure

Preamble/Postamble flags ensure frame-level
synchronization
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Synchronous Transmission Efficiency

• Example HDLC scheme uses a total of 48 bits for
  control, preamble, and postamble fields per
  frame
• With a data block consisting of 1000 characters
  (8-bits per character),
• ? Efficiency 8000/(800048) 99.4
• ? Overhead 48/8048 0.6
• Higher efficiency and lower overhead compared to
  asynchronous

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Errors in Digital Transmission

• Error occurs when a bit is altered between
  transmission and reception (0 ? 1 or 1 ? 0)
• Two types of errors
• Single bit errors
• One bit altered
• Isolated incidence, adjacent bits not affected
• Typically caused by white noise
• Burst errors
• Contiguous sequence of B bits in which first,
  last, and any number of intermediate bits are in
  error
• Caused by impulse noise or fading (in wireless)
• More common, and more difficult to handle
• Effect is greater at higher data rates
• What to do about these errors
• Detect them (at least, so we can ask TX to
  retransmit!)
• Correct them (if we can)

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Error Detection Correction Motivation

• Assume NO error detection or correction Number
  of erroneous frames received would be
  unacceptable
• Hence, for a frame of F bits,
• Prob frame is correct (1-BER)F Decreases
  with increasing BER F
• Prob frame is erroneous 1 - (1-BER)F Frame
  Error Rate (FER)

A frame of F bits
All bits must be Correct!
Prob 1st bit in error BER Prob 1st bit
correct 1-BER
Prob 2nd bit in error BER Prob 2nd bit
correct 1-BER
Prob Fth bit in error BER Prob Fth bit
correct 1-BER
All bits must be Correct!
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Motivation for Error Detection Correction
Example

• ISDN specifies a BER 10-6 for a 64kbps channel
• Frame size F 1000 bits
• What is the FER?
• FER 1 (1 BER)F 1 (0.999999)1000 10-3
• Assume a continuously used channel
• How many frames are transmitted in one day
  Number of frames/day (64,000/1000) 24 3600
• 5.5296 106
• How many erroneous frames/day?
• 5.5296 106 10-3 5.5296 103
• Typical requirement Maximum of 1 erroneous frame
  /day!
• i.e. frame error rate is too high!
• ? We definitely need error detection
  correction

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Frame Error Probabilities
1 0 1 0 1 0 0 0 1 0 1 0 0 0 1
P1
1 - P1
1000
Correct
Erroneous
With an error detection facility
900
100
Errors, Undetected
Errors, Detected
P2
P3
20
80

• P1 P2 P3 1
• Without error detection facility P3 0, and
• P2 1 P1

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Error Detection Techniques

• Two main error detection techniques
• Parity Check
• Cyclic Redundancy Check (CRC)
• Both techniques use additional bits that are
  added to the payload data by the transmitter
  for the purpose of error detection

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Error Detection Implementation
Mismatch Error Detected
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Parity Check

• Simplest error-detection scheme
• Appending one extra bit
• Even Parity Will append 1 such that the total
  number of 1s is even
• Odd Parity Will append 1 such that the total
  number of 1s is odd
• Example If an even-parity is used, RX will check
  if the total number of 1s is even
• If it is not ? error occurred
• Note even number of bit errors go undetected

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Cyclic Redundancy Check (CRC)

• Burst errors will most likely go undetected by a
  simple parity check scheme
• Instead, a more elaborate technique called Cyclic
  Redundancy Check (CRC) is typically implemented
• CRC appends redundant bits to the frame trailer
  called Frame Check Sequence (FCS)
• FCS is later utilized at RX for error detection
• In a given frame containing n bits, we define
• k number of original data bits
• (n k) number of bits in the FCS field (i.e.
  additional bits)
• So, that the total frame length is k (n k)
  n bits

D (k)
FCS (n-k)
1 0 1 0 0 0 1 1 0 1
01110
T(n)
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CRC Generation

• CRC generation is all about finding the FCS given
  the data (D) and a divisor (P)
• There are three equivalent ways to generate the
  CRC code
• Modulo-2 Arithmetic Method
• Polynomial Method
• Digital Logic Method

D (k)
FCS or F (n-k)
1 0 1 0 0 0 1 1 0 1
01110
T (n)
110101
P (n-k1)
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Modulo 2 Arithmetic

• Binary arithmetic without carry
• Equivalent to XOR operation
• i.e
• 0 ? 0 0 1 ? 0 1 0 ? 1 1 1 ? 1 0
• 1 ? 0 0 0 ? 1 0 1 ? 1 1
• Examples

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CRC Error Detection Process

• Given k-bit data (D), the TX generates an (n
  k)-bit FCS field (F) such that the total n-bit
  frame (T) is exactly divisible by some
  (n-k1)-bit predetermined devisor (P) (i.e. gives
  a zero remainder)
• In general, the received frame may or may not be
  equal, in value, to the sent frame
• Let the received frame be (T)
• In error-free transmission T T
• The RX then divides (T) by the same known
  divisor (P) and checks if there is any remainder
• If division yields a remainder then the frame is
  erroneous
• If the division yields zero remainder then the
  frame is error-free unless many erroneous bits in
  T resulted in a new exact division by P
• (This is very unlikely but possible, causing an
  undetected error!)

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CRC Generation
T 2 (n k) ? D F
(n-k) left shifts (multiplications by 2)
Data D
?
LSB

• P is 1-bit longer than F

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CRC Generation

• T 2(n k) ? D F, What is F that makes T
  divides P exactly ?
• Claim F is the remainder obtained from dividing
  2(n k) ? D by divisor P
• where Q is the quotient and F is the remainder
• If this is the correct F, T should now divide P
  with Zero remainder
• Note For F to be a remainder when dividing by P,
  it should be 1-bit smaller

(1)
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CRC Generation Modulo-2 Arithmetic Method

• At TX CRC Generation (using previous rules)
• Multiply 2(n k) ? D (left shift by
  (n-k) bits)
• Divide 2(n k) ? D / P
• Use the resulting (n k)-bit remainder as the
  FCS
• At RX CRC Checking RX divides the received T
  (i.e. T) by the known divisor (P) and checks if
  there is any remainder

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Example Modulo-2 Arithmetic Method

• Given
• D 1 0 1 0 0 0 1 1 0 1
• P 1 1 0 1 0 1
• Find the FCS field
• Solution
• First we note that
• The size of the data block D is k 10 bits
• The size of P is (n k 1) 6 bits
• ? Hence the FCS length is n k 5
• ? Total size of the frame T is n 15 bits

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Example Modulo-2 Arith. Method

• Solution (continued)
• Multiply 2(n k) ? D
• 2(5) ? 1 0 1 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1
  0 0 0 0 0
• This is a simple shift to the left by five
  positions
• Divide 2(n k) ? D / P (see next slide for
  details)
• 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 1 0 1
  yields
• Quotient Q 1 1 0 1 0 1 0 1 1 0
• Remainder R 0 1 1 1 0
• So, FCS R 0 1 1 1 0 Append it to D to get
  the full frame T to be transmitted
• T 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0
• M FCS

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Example Modulo-2 Arith. Method
of bits lt of bits in P, ? result of division
is 0
Checks you should do (exercise) - Verify
correct operation, i.e. that 2(n-k)D PQ R -
Verify that obtained T (101000110101110) divides
P (110101) exactly (i.e. with zero remainder)
FCS F
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Problem 6-12

• For P 110011 D 11100011, find the CRC

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Chances of missing an error by CRC error detection

• Let E be an n-bit number with a bit 1 at the
  position of each error bit error occurring in T
• Error occurring in T causes bit reversal
• Bit reversal is obtained by XORing with 1
• So, received Tr T ? E
• Error is missed (not detected) if Tr is divisible
  by P
• Since T is made divisible by P, this requires
  that E is also divisible by P!.
• That is a bit unlikely!

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CRC Generation Polynomial Method

• A k-bit word (D) can be expressed as a polynomial
  D(x) of degree (k-1) in a dummy variable x, with
• The polynomial coefficients being the bit values
• The powers of X being the corresponding powers of
  2
• bk-1 bk-2 b2 b1 b0 ? bk-1Xk-1 bk-2Xk-2
  b1X1 b0X0
• where bi (k-1 i 0) is either 1 or 0
• Example1 an 8 bit word D 11011001 is
  represented as D(X) x7x6x4x31
• Ignore polynomial terms corresponding to 0 bits
  in the number

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CRC Mapping Binary Bits into Polynomials

• Example2 What is x4D(x) equal to?
• x4D(x) x4(x7x6x4x31)
  x11x10x8x7x4, the equivalent bit pattern is
  110110010000 (i.e. four zeros appended to the
  right of the original D pattern)
• Example3 What is x4D(x) (x3x1)?
• x4D(x) (x3x1) x11x10x8x7x4 x3x1,
  the equivalent bit pattern is 110110011011 (i.e.
  pattern 1011 x3x1 appended to the right of
  the original D pattern)

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CRC Generation The Polynomial Way
Polynomial
Binary Arithmetic

• T(X) X(n k) ? D(X) F(X)

• T 2(n k) ? D F

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CRC Calculation - Procedure

1. Shift pattern D(X), (n-k) bits to the left, i.e.
   perform the multiplication X(n-k)D(X)
2. Divide the new pattern by the divisor P(X)
3. The remainder of the division, R(X) (i.e. n-k
   bits), is taken as FCS
4. The frame to be transmitted T(X) is
   X(n-k)D(X) FCS

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Example of Polynomial Method

• D 1 0 1 0 0 0 1 1 0 1 (k 10)
• P 1 1 0 1 0 1 (n k 1 6)
• n k 5 ? n 15
• Find the FCS field
• Solution
• D(X) X9 X7 X3 X2 1
• P(X) X5 X4 X2 1
• X5D(X)/P(X) (X14 X12 X8 X7 X5)/(X5 X4
  X2 1)
• This yields a remainder R(X) X3 X2 X
  (details on next slide)
• i.e. F 01110
• R is n k 5-bit long ? Remember to indicate
  any 0 bits!

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Example of Polynomial Method
F R
D
1 0 1 0 0 0 1 1 0 1
01110
T
Insert 0 bits to make 5 bits
110101
P
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Choice of P(X)

• How should we choose the polynomial P(X)
  (or equivalently the divisor P)?
• The answer depends on the types of errors that
  are likely to occur in our communication link
• As seen before, an error pattern E(X) will be
  undetectable only if it is divisible by P(X)
• It can be shown that all the following error
  types are detectable
• All single-bit errors, if P(X) has two terms or
  more
• All double-bit errors, if P(X) has three terms or
  more
• Any odd number of errors, if P(X) contains the
  factor (X1)
• Any burst error whose length is less than the FCS
  length (n k)
• A fraction (1-2-(n-k-1) ) of error bursts of
  length (n-k1)
• A fraction (1-2-(n-k) ) of error bursts of
  length gt (n-k1)

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Choice of P(X)

• In addition, if all error-patterns are equally
  likely, and r n - k length of the FCS,
  then
• For a burst error of length (r 1), the
  probability of undetected error is 1/2(r 1)
• For a longer burst error i.e. length gt (r 1),
  the probability of undetected error is 1/2 r
• There are four widely-used versions of P(X)
• CRC-12 P(X) X12 X11 X3 X2 X 1
• (r 13 -1 12)
• CRC-16 P(X) X16 X15 X2 1 (r
  17 -1 16)
• CRC-CCITT P(X) X16 X12 X5 1
• CRC-32 P(X) X32 X26 X23 X22 X16 X12
  X11 X10 X8 X7 X5 X4 X2 X 1
• (r 33 -1 32)

FCS is 1-bit shorter than P
FCS Size
P(X) always starts with 1
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Some CRC Applications

• CRC-8 and CRC-10 (not shown) are used in ATM
• CRC-12 is used for transmission of 6-bit
  characters. Its FCS length is 12-bits
• CRC-16 CRC-CCITT are used for 8-bit characters
  in the US and Europe respectively
• Used in HDLC
• CRC-32 is used for IEEE 802.3 LAN standard

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CRC Generation Digital Logic

• k 10 (size of D) (known data to be TXed)
• n k 1 6 size of P (known divisor) P (X)
  X5X4X21 (110101)
• n k 5 size of FCS (to be determined at TX)
• n 15

• 5-element left-shift register
• Initially loaded with 0s
• After n left shifts, register will contain the
  required FCS

Always An XOR at C0
P X5X4X2X0

• Divisor is hardwired as feedback connections
• via XOR gates into the shift register cells
• Starting at LSB, for the first (n-k) bits of P,
  add an XOR only for 1 bits

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CRC Generation at TX
P X5X4X2X0
Start with Shift Register Cleared to 0s
C0 in
C2 in
C4 in
MSB
D
Inputs formed with Combination Logic
MSB
FCS generated in the shift register after n (15)
shift steps
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CRC Checking at RX
P X5X4X2X0
Start with Shift Register Cleared to 0s
C0 in
C2 in
C4 in
MSB
15 bits
D
D
Received Frame, T
MSB
FCS
Inputs formed with Combination Logic
0s in the shift register after n (15) shift
steps (if no errors)
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Problem 6-13

• A CRC is constructed to generate a 4-bit FCS for
  an 11-bit message. The generator polynomial is
  X4X31
• Draw the shift register circuit that would
  perform this task
• Encode the data bit sequence 10011011100
  (leftmost bit is the LSB) using the generator
  polynomial and give the code word
• Now assume that bit 7 (counting from the LSB) in
  the code word is in error and show that the
  detection algorithm detects the error

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Problem 6-13 Solution
Input data

• a)

?
?
C0
C1
C2
C3
P(X) X4X31
b) Data (D) 1 0 0 1 1 0 1 1 1 0 0 D(X) 1
X3 X4 X6 X7 X8 X4D(X) X12 X11 X10
X8 X7 X4 T(X) X4M(X) R(X) X12
X11 X10 X8 X7 X4 X2 Code
0 0 1 0 1 0 0 1 1 0 1 1 1 0 0 c) Code in error
0 0 1 0 1 0 0 1 1 0 0 1 1 0 0 yields a
nonzero remainder ? error is detected
LSB
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Error Correction

• Once an error is detected, what action can RX
  take? (i.e. I found an error, now what? ?)
• Two alternatives
• RX asks for a retransmission of the erroneous
  frame
• Adopted by data-link protocols such as HDLC and
  transport protocol such as TCP
• A Backward Error Correction (BEC) method
• RX attempts to correct the errors if enough
  redundancy exists in the received data
• TX uses Block Coding to allow RX to correct
  potential errors
• A Forward Error Correction (FEC) method
• Use in applications that leave no time for
  retransmission, e.g. VoIP.

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Error Correction vs. Error Control

• Backward error correction by retransmission is
  not recommended in the
  following cases
• Error rate is high (e.g. wireless communication)
• Will cause too much retransmission traffic ?
  network overloading
• Transmission distance is long (e.g. satellite,
  submarine optical fiber cables)
• Network becomes very inefficient (Not utilized
  properly)
• Usually
• Error Correction methods Those that use FEC
  techniques
• Error Control methods Those that use
  retransmission