A Low-Cost CMOS Compatible Serpentine-Structured Polysilicon-Based Microbolometer Array

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A Low-Cost CMOS Compatible Serpentine-Structured
Polysilicon-Based Microbolometer Array
ERAN SOCHER YEHUDA SINAI and YAEL NEMIROVSKY
KIDRON MICROELECTRONICS RESEARCH
CENTER DEPARTEMENT OF ELECTRICAL
ENGINEERING TECHNION - ISRAEL INSTITUTE OF
TECHNOLOGY
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OVERVIEW

• CMOS Compatible Microbolometers
• Serpentine CMOS Bolometer Design
• CMOS Bolometer Fabrication
• Sensor Array CMOS Readout Design
• Measured Results
• Summary

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MICROBOLOMETER PRINCIPLE OF OPERATION
resistor
membrane
air gap
CMOS readout
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MICROBOLOMETER SIGNAL

• For a voltage biased bolometer, the current
  responsivity and the response time are

• For a current biased bolometer, the voltage
  responsivity and the response time are

• The temperature rise is mainly due to electrical
  heating, which may vary in time when using pulsed
  bias

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MICROBOLOMETER SNR

• The Noise Equivalent Power of the bolometer,
  e.g. for voltage bias is limited by temperature
  fluctuations, Johnson noise and 1/f noise

• The resulting Noise Equivalent Temperature
  Difference is

Johnson noise approximation
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CMOS COMPATIBILITY OF BOLOMETERS

• Conventional microbolometer arrays are based on
  realizing non-CMOS layers, usually structured as
  suspended membranes, on top of a processed CMOS
  wafer
• Common drawbacks include
• Non uniformity of resistors
• Chemical and temperature non-compatibility with
  CMOS
• Increased cost and complexity
• Our design is based on using standard CMOS
  materials for integrated microbolometers with
  simple postprocessing that enables realization of
  low-cost sensor arrays

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SERPENTINE CMOS BOLOMETERS

• We use the standard polysilicon layer as the
  temperature-sensitive resistance and the process
  dielectric layers as the structural and IR
  absorbing layers
• A suspended serpentine structure is used in
  order to increase the effective thermal
  resistance for a given pixel area

• The whole area of the structure serves as both
  thermal isolation and absorbing layer
• Definition of the structure is done as part of
  the CMOS process

polysilicon
dielectrics
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STRUCTURE ANALYSIS

• The bolometers under study here are distributed
  microbridge structures that can be modeled using

I
x
xL
x0
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STRUCTURE RESPONSIVITY

• The steady-state normalized temperature response
  can be approximated as

• The resulting voltage responsivity can be
  approximated by integration along the structure
  as

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STRUCTURE NEP AND RESPONSE TIME

• Assuming a Johnson limiting noise, the NEP can
  be approximated as

• The time response is composed from an infinite
  number of response times

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PROCESS FLOW

• The first phase of the process a standard
  AMI1.5mm CMOS process for readout circuits and
  pre-sensors
• The second step is bulk silicon isotropic
  micromachining using SF6/O2 RIE
• The third step is gold-black deposition for
  absorption enhancement

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FABRICATED DEVICES

• Sensor structure is a microbridge of highly
  doped polysilicon enclosed in the CMOS dielectric
  layers
• A serpentine structure is used to maximize the
  total length
• Dielectric mechanical supports were added with
  minimal thermal effect

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SENSOR ARRAY READOUT AND LAYOUT

• A test-chip was designed based on the current
  integration mode concept
• It includes a 1616 bolometer array with
  integrator per column
• Timing circuits include a fast SR for individual
  bias charge from on-chip 5bit DAC, slower SR for
  row integration and output multiplexing to a
  single output achieving a frame-rate of 60Hz

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SENSOR ARRAY READOUT AND LAYOUT

• A test-chip was designed based on the current
  integration mode concept
• It includes a 1616 bolometer array with
  integrator per column
• Timing circuits include a fast SR for individual
  bias charge from on-chip 5bit DAC, slower SR for
  row integration and output multiplexing to a
  single output

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FABRICATED DEVICES

• A 1616 sensor array was also fabricated with
  integrated CMOS readout circuitry
• Pixel size is 100100 mm2, limited mainly by the
  CMOS process feature size, and includes the
  bolometer and PMOS transistors for biasing and
  multiplexing

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DEVICE CHARACTERIZATION

• Average bolometer resistance was about 10-20
  higher than designed (10kW), but non-uniformity
  was better than 1
• A metal-like positive temperature coefficient of
  resistance was measured as about 0.1/K
• Noise measurements showed 1/f noise to be
  negligible with a 1V bias down to 0.1Hz,
  corresponding to KFlt10-16

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DEVICE CHARACTERIZATION

• I-V curves of released devices are measured to
  characterize the effective thermal resistance
• The effect of mechanical support was minimal,
  but addition of the first metal layer enabled
  thermal resistance smaller by an order of
  magnitude for blind sensors

Gunsupported5.710-7 W/K Gsupported5.910-7
W/K Gblind6.310-6 W/K
Blind pixel
Pixel with supports
Unsupported pixel
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ELECTRO-OPTICAL CHARACTERIZATION

• Bolometers are voltage biased with the current
  read by a lock-in amplifier through a
  transimpedance amplifier
• Sensors are irradiated by a black-body through a
  chopper
• The NETD of the sensor is estimated as 210mK for
  f/1 based on the measurements

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SUMMARY

• Novel polysilicon serpentine microbolometers
  were analyzed, designed, fabricated in standard
  CMOS technology and tested
• Characterization shows a response time of 14msec
  and a NETD of 210mK assuming f/1 optics and
  72msec integration time
• A 1616 array demonstrator was designed in
  standard CMOS technology with readout circuits
  including differential current integration and
  5bit DAC for individual pixel biasing to improve
  non-uniformity, which is currently under testing
• Use of a CMOS process with smaller feature size
  is expected to increase performance

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Questions?