DIMINISHING LINE COUPLED NOISE

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DIMINISHING LINE COUPLED NOISE
EE215B PROJECT

• ADVISOR PROF INGRID VERBAUWHEDE
• GUICHANG ZHONG, ZHIWEI XU

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PRESENTATION OVERVIEW

• Introduction
• Analysis of line coupled noise in VLSI
• Analysis of noise immunity in VLSI
• Physical Solution to diminish line coupled noise
• Current Steering Logic to diminish line coupled
  noise
• Differential Logic to diminish line coupled noise
• Summary

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INTRODUCTION

• Noises in VLSI
• Simultaneous Switching Noise (Ground Bounce,
  Delta I Noise)
• Line Coupled Noise (Crosstalk)
• Substrate Coupling Noise
• Effects of the noises in VLSI
• Compromising the function of circuit ( Digital
  logic error Analog accuracy lose)
• Sequential error (eg changing the cell delay)

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ANALYSIS OF LINE COUPLED NOISE

• Line coupled effects
• A simple model of line coupled effects

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THE METHOD TO LOWER THE LINE COUPLED NOISE

• Lower resistance of the line driver
• Lower coupled capacitor
• Longer input signal rising time
• Larger capacitor from the buses to ground
• Smaller swing of the input signal on aggressor

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LINE COUPLED EFFECTS TO COMMON CMOS VLSI

• Simple Line
• Coupled case
• Generated Noise
• and the effect on timing by line coupled noise

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ANALYSIS OF NOISE IMMUNITY IN VLSI

• Noise immunity of digital logic gates is how much
  the digital logic gates are affected by the noise

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POTENTIAL PHYSICAL SOLUTION TO DIMINISH LINE
COUPLED EFFECTS

• Increase separation between wires
• Place supply rails between wires
• Offset switching times of adjacent wires
• Arrange adjacent signals to travel in opposite
  directions
• Swizzling technique
• Ordering control signals

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ORDERING CONTROL SIGNAL
Cross-coupling effect on the victim wire from the
adjacent nets (a) the worst case and (b) the best
case
Delay comparison of the worst case and best case
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ORDERING CONTROL SIGNAL (EXAMPLE)
A 3-bit MUX example
Three different orderings
data
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ORDERING CONTROL SIGNAL (EXAMPLE)

• Layout Implementation

Order 2 (Commonly used scheme)
Order 3 (2.1 larger area)
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CURRENT STEERING LOGIC TO LOWER LINE COUPLED NOISE

• Current Steering Logic Inverter
• CSL inverter lower the line coupled noise because
  of small swing

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CURRENT STEERING LOGIC TO LOWER LINE COUPLED NOISE

• Line Coupled
• case
• Generated Noise
• and the effect on timing by line coupled noise

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DIFFERENTIAL LOGIC TO LOWER LINE COUPLED NOISE

• Differential Logic Structure and Noise magnitude
  pulse width plot

Differential inverter (buffer)
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DIFFERENTIAL LOGIC TO LOWER LINE COUPLED NOISE

• Generated Noise and the effect on timing by line
  coupled noise

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DIFFERENTIAL LOGIC TO LOWER LINE COUPLED NOISE

• Differential logic with swizzling technique

Comparison of delay before and after swizzling
Swizzling technique
Coupling capacitance 2Clat-gt1.5Clat
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SUMMARY

• Analyze and model the line coupled noise
• Physical solutions to diminish line coupled
  noise control signal ordering, swizzling,
• Propose Current Steering Logic to lower line
  coupled noise
• Propose Differential Logic to lower line coupled
  noise

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PROSPECTIVE RESEARCH TOPIC

• Dynamic logic is a candidate to lower line
  coupled noise from signal ordering view
• Algorithm level solutions to specific application
  (eg. reduce switching activities)

THANK YOU ALL!