IEEE 2015 VLSI A SUC-BASED FULL-BINARY 6-BIT 3.pptx

1
A SUC-BASED FULL-BINARY 6-BIT 3.1-GS/S
17.7-MWCURRENT-STEERING DAC IN 0.038 MM2
2
ABSTRACT

• A 6-bit full-binary compact and low-power
  current-steering digital-to-analog converter
  (DAC) designed for 60-GHz Wireless Personal Area
  Network applications is presented. The closely
  located circuit components based on the stacked
  unit cell minimize the parasitic capacitance and
  enhance the high-frequency dynamic linearity. The
  proposed binary structure realizes a compact DAC
  by eliminating the need for additional circuits,
  such as thermometer decoders, and thus reduces
  power consumption. A prototype 6-bit 3.1-GS/s
  full-binary DAC was fabricated in a 90-nm CMOS
  process. The DAC exhibits a spurious free dynamic
  range of gt37.2 dB up to 3.1 GS/s over the Nyquist
  input. The chip consumes 17.7 mW of power and
  occupies 0.038 mm2 of core size.

3
EXISTING SYSTEM

• There are two important design specifications for
  such applications 1) low power consumption and
  2) wideband linearity. Since most emerging
  technologies require mobile applications, low
  power is a primary requirement for DACs as well.
  Considering that the recently developed ADCs,
  unlike the traditional flash structures, such as
  those in, could achieve drastically reduced power
  consumption by eliminating the static power, the
  power consumption in current-steering DACs has
  not been reduced significantly. With the
  inevitable power consumption of the current
  sources, an appropriate approach to save power
  would be to optimize digital blocks.

4
PROPOSED SYSTEM

• The DAC core is composed of an
  array of 64 SUCs (that closely stacks all circuit
  elements related to the unit current sources
  operation, from current source to switch driver)
  in a single-in-line manner, and the buffers are
  used for the data and clock driving. Note that no
  nonessential building blocks such as
  pseudodecoder was utilized, and that the
  parasitic capacitance at the output of the
  current source is minimized. The width of SUC can
  be fitted desirably to that of the current source
  for a compact design. The MSB is composed of 32
  SUCs and 16 SUCs are used for the MSB-1, and so
  on.

5

• Thus, not only the current
  sources but also the circuitry related to them,
  such as switches and switch drivers, have the
  exact required weight with respect to the LSB
  unit segment. To drive the binary-weighted loads,
  the buffers for data are also designed to have
  corresponding weights by merging unit drivers in
  parallel e.g., the buffer for MSB is composed of
  parallel 32 unit buffers. Since each unit cell
  has an identical structure and only one global
  clock is used for all units, the switching
  characteristics will be identical regardless of
  which weight is being used. Thus, the dynamic
  nonlinearity from the timing misalignment will
  be inherently reduced.

6

• A concern may arise on the current
  matching of the single-in-line structure compared
  with the 2-D matrix design. However, in order to
  cancel out the gradient error that may exist, the
  SUCs are placed in a 1-D common centroid manner
  with the LSB segment in the center of the array.
  In addition, the modern CMOS processes provide
  significantly enhanced device matching
  characteristics compared with the previous
  designs, and random mismatch errors are known to
  be a weak function of the distance between the
  devices. The proposed SUC-based DAC structure
  encourages a compact chip area owing to the
  simplified core structure, and reduces the power
  consumption compared with the previous designs
  due to the minimalizing strategy (no nonessential
  blocks and minimum parasitic capacitances).

7
SOFTWARE REQUIREMENTS

• Xilinx ISE Design Suite 13.1
• Cadence-RTL Complier
• Cadence- encounter