IEEE 2015 VLSI AGING-AWARE RELIABLE MULTIPLIER DESIGN WITH ADAPTIVE HOLD LOGIC.pptx

1
AGING-AWARE RELIABLE MULTIPLIER DESIGN WITH
ADAPTIVE HOLD LOGIC
2
ABSTRACT

• Digital multipliers are among the most
  criticalarithmetic functional units. The overall
  performance of thesesystems depends on the
  throughput of the multiplier. Meanwhile,the
  negative bias temperature instability effect
  occurs whena pMOS transistor is under negative
  bias,increasing the threshold voltage of the pMOS
  transistor, andreducing multiplier speed. A
  similar phenomenon, positive biastemperature
  instability, occurs when an nMOS transistor is
  underpositive bias.

3

• Both effects degrade transistor speed, and in
  thelong term, the system may fail due to timing
  violations. Therefore,it is important to design
  reliable high-performance multipliers. In this
  paper, an aging-aware multiplier is designed with
  anovel adaptive hold logic (AHL) circuit. The
  multiplier is able toprovide higher throughput
  through the variable latency and canadjust the
  AHL circuit to mitigate performance degradation
  thatis due to the aging effect. Moreover, the
  proposed architecturecan be applied to a column-
  or row-bypassing multiplier.

4

• Theexperimental results show that our proposed
  architecture with16 16 and 32 32
  column-bypassing multipliers can attain upto
  62.88 and 76.28 performance improvement,
  respectively, compared with 1616 and 3232
  ?xed-latency column-bypassingmultipliers.
  Furthermore, our proposed architecture with 16
  16and 32 32 row-bypassing multipliers can
  achieve up to 80.17and 69.40 performance
  improvement as compared with 1616and 32 32
  ?xed-latency row-bypassing multipliers.

5
EXISTING METHODS

• 1. Guard banding and gate oversizing technique to
  mitigate the aging effect 2. NBTI optimization
  which considered the path sensitization, dynamic
  voltage scaling and body biasing technique to
  reduce the power or extend circuit life. But this
  method increases the delay.3. Variable latency
  adder with speculation technique for error
  detection and correction which increases the
  area. 4. Design of variable latency multiplier
  with the help of booth technique, which increases
  the area because of recoding circuitry.

6
PROPOSED METHOD AGING AWARE RELIABLE MULTIPLIER

• An aging-aware reliable multiplier is designed
  with a novel adaptive hold logic (AHL) circuit.
  The multiplier is based on the variable-latency
  technique and can adjust the AHL circuit to
  achieve reliable operation under the in?uence of
  NBTI and PBTI effects. The AHL circuit can decide
  whether theinput patterns require one or two
  cycles and can adjustthe judging criteria to
  ensure that there is minimum performancedegradatio
  n after considerable aging occurs. The aging
  aware reliable multiplier is designed based on
  Row/Column bypass multiplier which reduces the
  activity power. Razor flipflops are used to
  detect the timing violation.

7
(No Transcript)
8
ADVANTAGES

• 1. Increases the speed
• 2. Reduces the area